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ADC12D1800RB NonDES I and Q Sample Alignment Issue

Other Parts Discussed in Thread: WAVEVISION5, ADC10D1000, ADC12D1800

Hello,


Sorry if this should be a new thread, wasn't sure.  I've made good progress using the board in my system using just the I channel.  I am now feeding signals in the I and Q channel. In nonDES I and Q mode, 16K samples mode, it appears the board is sampling 8K from the I Channel and then sequentially sampling 8K from the Q channel.  I would like to sample the two channels as close in time as possible. Is there a setting for an interlace sampling? I've verified my I and Q inputs separately using an o-scope to make sure the timings and triggers are all set up properly.   I've also noticed the Q channel will not output anything when trying 32K samples mode, only the I channel shows the signal.  Any ideas? Thank you for any help you can provide.

Justin

  • Hi Justin

    I've moved this into a new thread for clarity.

    I believe the primary issue you are seeing is caused by a bug in the FPGA image for that board. The original design didn't handle data storage properly for the NonDES I and Q mode of operation. I thought that an updated fixed version should have been included in the current Wavevision 5 installer, but that doesn't seem to be the case. To resolve this part of the problem, please do the following.

    1) Navigate to the following folder (assuming a standard installation on Windows 7):

    C:\Program Files (x86)\National Semiconductor\WaveVision5\hardware\fpga_images

    2) In this folder, rename the following file, adding .bak as a suffix to prevent loss if you need to revert.

    Original name "adc10d1000_xc4vlx25_adc12d1600rfrb.bit"

    New name "adc10d1000_xc4vlx25_adc12d1600rfrb.bit.bak"

    Trust me, this is the correct file for the ADC12D1800RB. A number of similar boards all use this common firmware and we save some space this way.

    3) Copy this file below (inside the .zip) into that same folder. It will take the place of the one you have renamed.

    adc10d1000_xc4vlx25_adc12d1600rfrb.zip

    Once this new file is in place, power cycle the board, re-connect the USB cable and re-start Wavevision 5. Data captures in NonDES I and Q mode should be properly phase aligned.

    The second part of your issue relates to how I and Q (two channel mode) data is displayed in Wavevision 5. To properly display both channels in the same image you need to change one setting. Once NonDES I and Q mode is selected, and data has been captured, navigate to the Channels tab on the left side of the screen. In that tab uncheck the box labeled "Automatically hide inactive channels".

    Once you do this step the second channel in Green should show up along with the first channel in Red.

    When you perform a new data capture both channels should update. I checked a similar board here and this should work even for captures up to 32k samples, but let us know if you still have any issues.

    Best regards,

    Jim B

  • Jim,

    That seem to do the trick! Thank you for the support.

    Regards,

    Justin

  • I'm using an ADC12D1800RFRB4 EvalBoard (with an ADC12D1800) and would like to use the FPGA source code as the starting point for some of my own prototyping work.
    Therefore I downloaded a corresponding ZIP file (snac040a, ADC12D1x00RFRB DesignPackage), and compiled the code with both Xilinx ISE 14.7 (the latest available version)
    and ISE 12.2 (based on the info in the project file I got the impression that this was the version used when the project was created). The compilation succeeds, but
    in both cases I get some "critical timing violations" and what's worse: when I load one of these "home compiled" bit files, WaveVision5 reports a hardware failure
    because there is no lock on DCLK. Another thing that is puzzling: the bit file that you posted here has an older time stamp (16.3.2013) than the one which got installed
    with WaveVision5 (15.7.2014). Could you provide me with the latest HDL sources and Xilinx project files (ideally for ISE 14.7) such that I can recompile the bit file myself?

    Best Regards,
    Matthias

  • Hi Matthias,

    Please find the attached latest source files for ADC12D1X00RFRB.

    Regards,

    Neeraj Gill

    ADC12D1800.zip

  • Hi Neeraj

    Thanks for your post. Unfortunately I got sidetracked with lots of other stuff and just got back to this problem today. It seems that the ZIP file you provided corresponds to the code included in snac040a and therefore shows the same problems I discribed in my original post. Isn't there any other source code/project settings available that can actually be used to compile a working FPGA binary?

    Best Regards,

    Matthias