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DAC8564 Internal regulator collapsing

Deepika Ranade86842
Prodigy 140 points
Other Parts Discussed in Thread: DAC8564, OPA2277

I am trying to communicate with DAC8564. My SPI speed is 16MHz, supply voltage is 3.3V. I have 4 DAC8564 IC's on a single SYNCbar line. Enable and LDAC pins are tied to ground. The internal regulator generates correct Vref of 2.5V on powerup. However as soon as I write data to it, the Vref collapses to 1.5V. I am not using external regulator. I am not sending power down command. What am I doing wrong?

  • 0
    TI__Genius 10615 points

    Hi Deepika,

    This is very strange behavior. I have a few questions in order to be able to debug your issue.

    Can you share the schematic of your design?

    Are the reference pins for the each of the DAC8564s connected to anything?

    What is the load on the output of each of the channels? What code are you writing to it?

  • 0 in reply to Eugenio Mejia
    Prodigy 140 points

    Hi Eugenio,

    The only thing that is connected to the reference pins is a capacitor.

    The output channels connect to NINV input of Opamp OPA2277.

    I am sending commands interactively through a Xilinx FPGA. The AVDD of the DAC8564 is powered up first, followed by the AVDD to the FPGA. The FPGA pins connected to SCLK, and DIN are logic high when the FPGA is at power-on reset,  and go to zero once FPGA is out of reset. The SCLK and DIN are high for 1.5sec during the startup (SYNC pin is high for the entire duration except SPI write). Could this be the cause of the issue?

  • 0 in reply to Deepika Ranade86842
    TI__Genius 10615 points

    Deepika Ranade86842 said:
    The only thing that is connected to the reference pins is a capacitor.

    The reference pins are not connected to each other correct?

    Deepika Ranade86842 said:
    The output channels connect to NINV input of Opamp OPA2277.

    Each of the DAC channels is connected to a single NINV input of the OPA2277, correct? Meaning that you are using 8x OPA2277?

    It would be very helpful to see a schematic. If you would rather share this privately, is it okay to contact you to your registered E2E email?

    Deepika Ranade86842 said:
    The SCLK and DIN are high for 1.5sec during the startup (SYNC pin is high for the entire duration except SPI write). Could this be the cause of the issue?

    I don't think this will be an issue.
    Can you also share an oscilloscope capture of the SPI write sequence. This way I can verify that everything is correct.

  • 0 in reply to Eugenio Mejia
    Prodigy 140 points

    Hi Eugenio,

    I am now sending a few commands after power-up to enable internal reference in default mode + sending a broadcast command to load all DAC registers with 0. This seems to solve the issue. My guess is somehow SPI circuit got stuck/ locked, and we needed to send a dummy SPI command to get to correct operation.

    Yes each of the reference connects to a separate capacitor. They are not connected to each other.

    The DAC outputs each go to a separate NINV of different OPA2277s.

    This is my current SPI. I have further reduced the frequency of SPI.

    This was my previous screenshot when the vref starts collapsing soon after the SPI command.

  • 0 in reply to Deepika Ranade86842
    TI__Genius 10615 points

    Deepika Ranade86842 said:
    I am now sending a few commands after power-up to enable internal reference in default mode + sending a broadcast command to load all DAC registers with 0. This seems to solve the issue. My guess is somehow SPI circuit got stuck/ locked, and we needed to send a dummy SPI command to get to correct operation.

    The DAC8564, enables the internal reference by default, and powers on to zero scale by default. Can you share the codes that you are sending? I want to verify that everything is correct there as well.

    The SPI plots that you sent me, do look like a correct write and update sequence. However the false edges on the IO signals are very close to the IO limits of the DAC pins. Is there any way you can test the behavior of the device with cleaner SPI edges? At least just for debugging purposes.

  • 0 in reply to Eugenio Mejia
    Prodigy 140 points

    Hi Eugenio,

    I am using these commands:

                    ##put reference in default state
                    self.FPGA.write("DAC", [0x010000])

                    ##broadcast command to reset all dacs to SR data==0x0000
                    self.FPGA.write("DAC", [0x340000])

    A cleaner SPI capture: Sorry about the earlier picture, I wasnt using a local ground that time, so it looked like false edges could be violating VIH/ VIL.