• State Resolved
  • Locked Locked
  • Replies 13 replies
  • Answers 4 answers
  • Subscribers 46 subscribers
  • Views 1197 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS7822 / About DCLOCK

ACGUY
Guru 11170 points
Other Parts Discussed in Thread: ADS7822

Hi all,

Please let me know about DCLOCK of ADS7822.

I have questions are as follows;

 - How much the upper limit of CDLOCK?

 - What is "fCLK"?

Also, our customer can not output the data.

Please see the picture.

Please let me know the cause.

Regards,

Nagai.

  • 0
    TI__Expert 8945 points
    Hello Mr. Nagai,

    The DCLOCK & fCLK refer to the same clock.

    Based on Vcc, you can feed the maximum DCLOCK as 16*throughput_rate.

    e.g. At Vcc = 2.7V, max throughput_rate = 75kHz, hence max DCLOCK = 1.2MHz

    similarly at Vcc = 5V, max DCLOCK = 16*200kHz = 3.2MHz

    I did not receive the picture for the "No output data" condition. Please resend the same and share more information regarding the ADC configuration.

    Thanks & Regards,
    Shridhar.
  • 0 in reply to Shridhar%20More
    Guru 11170 points

    Hi Mr. Shridhar,

    Thank you for reply.

    I have a question.

    If CE = High, DCLOCK is must be a Low?

    Not described on datasheet about state specification of DCLOCK.

  • 0 in reply to ACGUY
    TI__Expert 8945 points
    Hello Mr. Nagai,

    When CE = HIGH, the DCLOCK can have any state

    i.e, HIGH or LOW or toggling clock limited to max speed for particular Vcc.

    If the DCLOCK is toggling it will result in higher quiescent current. This is mentioned in the quiescent power section of the Electrical Characteristics table for Vcc = 2.7V. The footnote 4 & 5 describe the same.

    Thanks & Regards,
    Shridhar.
  • 0 in reply to Shridhar%20More
    Guru 11170 points

    We apologize that our explanation makes you confuse.

     

    We would like to ask the following;

     

    ＜Question＞

    When /CS is changes from High to Low(as the datasheet Figure 22. Basic Timing Diagrams), DCLOCK must be set Low, mustn't it?

    Timing Specification "tCSD(/CS falling to DCLOCK low)" shows max 0ns.

    As our recognition, in case of starting I/F(communication start), does it mean that DCLOCK must be set Low?

     

    Our customer could not acquire the data from DOUT when the DCLOCK was "HIGH - start".

    However, when the DCLOCK was "Low - start", our customer could acquire the data from DOUT.

     

    Is this correct?

     

    Kind regards,

  • 0 in reply to ACGUY
    TI__Expert 8945 points
    Hello Mr. Nagai,

    This is an interesting observation.

    According to Figure 22, the DCLOCK state is not defined (grey color) when CS goes low, while tCSD is specified as max 0ns.

    Based on the Figure, you should be okay with DCLOCK = HIGH, while the timing table does not agree with it. I need to check with design team if we have any other information on this.

    I would like to know when DCLOCK = HIGH, whether the captured data is wrong or you do not observe any toggling.

    If possible can you capture the CS, DCLOCK & DOUT pin waveforms on a oscilloscope for DCLOCK = HIGH & DCLOCK = LOW conditions.

    Please share these waveforms for further analysis.

    Thanks & Regards,
    Shridhar.
  • 0 in reply to Shridhar%20More
    Guru 11170 points

    Hi Mr. Shridhar,

    Attach the waveform file. Please see it.

    Left;
     - When the DCLOCK was "High - start", DOUT was all Low.
    Right
     - When the DCLOCK was "Low - start", able to output the DOUT.

    Our customer was not able to output the data from the ADS7822.
    However they was able to output the data by inverted the DCLOCK.

    Best Regard,

    Nagai

     ADS7822-DCLK.pdf

  • 0 in reply to ACGUY
    TI__Expert 8945 points
    Hello Mr. Nagai,

    Thanks for sharing the information. No toggling of DOUT is an unexpected behavior & we will have to reproduce the issue in our lab before we can debug this further.

    I do not have a EVM for this device since this is a very old device. I will try to get a quick spin board done to check the digital activity. I will get back to you once the testing is done. This will take few days.

    Meanwhile, can you confirm if this issue is observed on multiple devices or this is stand alone occurrence.

    Thanks & Regards,
    Shridhar.
  • 0 in reply to Shridhar%20More
    Guru 11170 points

    Hi Mr. Shridhar,

    Our customer tried two devices.

    Both had the same result.


    Thanks & Regards,

    Nagai.

  • 0 in reply to Shridhar%20More
    Guru 11170 points
    Hello Mr. Shridhar,

    Did you able to get the result about it?
    I waiting for your good answer. I'd greatly appreciate your cooperation.

    Best regards,
    Nagai.
  • 0 in reply to ACGUY
    TI__Expert 8945 points
    Hello Mr. Nagai,

    We never had an EVM for this device. I have done a quick spin board to verify only the digital functionality. The board is getting manufactured.

    The software to test the digital functionality is also being modified.

    Once I have the board & the device samples in hand I will quickly verify this & get back to you. This may need another 4 days.

    Thanks & Regards,
    Shridhar.
  • 0 in reply to Shridhar%20More
    TI__Expert 8945 points
    Hello Mr. Nagai,

    I am assembling a quick spin board with ADS7822 samples. I expect to get back to you with my observations on Monday.

    Thanks & Regards,
    Shridhar.
  • 0 in reply to Shridhar%20More
    Guru 11170 points

    Hello Mr. Shridhar,

    We can't proceed without your response.

    I am looking forward to hearing from you at your earliest convenience. Thank you.

    Best regards,
    Nagai.

  • 0 in reply to ACGUY
    TI__Expert 8945 points
    Hello Mr. Nagai,

    I have sent you a request. Please accept the same & we will start separate communication to discuss results further.

    Thanks & Results,
    Shridhar.