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ADS5485 Maximum Analog Input Level

Gavin Teague
Intellectual 275 points
Other Parts Discussed in Thread: ADS5485

Hello

I am using the ADS5485 ADC in a system. According to the datasheet, the maximum analog input signal to GND is (–0.3 to (AVDD5 + 0.3)). I assume that this is where the protection diodes become forward biased and start conducting.

In normal operation, the analog input level to the ADS5485 ADC will be far less than this. However, our system needs to be able to handle the occasional 'fault' condition where the magnitude of the analog input could exceed (AVDD5 + 0.3). The system must be able to survive these fault conditions and the ADC should not be damaged as a result.

If possible, I would like to find out if there is a specification for the maximum rated current that the protection diodes can safely handle. I am hoping that I would be able to use this to set the source impedance of the ADC driver so that if a fault occurs and the protection diodes start conducting, that the maximum rated current is not exceeded.

The fault condition would be for an 'AC' input. The sample clock frequency is 80MHz and the I/F frequency is 60MHz.

Thanks

 

  • 0
    TI__Mastermind 29220 points

    Hi,

    I can ask the design team if they could recommend a safe current limit on such an occurrence.

    What would be the amplitude of the analog input during the time that the supplies are at zero?  I assume it would be within normal full scale range.  By AC input, I take to mean that the signal is not a constant level above the spec, like a DC signal which is a help here.  But then you also state the input is 60MHz, so by AC input do you mean AC coupled so that the ADC is free to bias the device to VCM?  That would help also.

    I also would expect that this type of absolute max specification is concerned with what happens when the ESD diodes turn on.  When this happens, if the signal source were 'unlimited' in its ability to source current then while the ESD diodes are on the device will try to power itself up through the ESD diodes that are on, and that could be a lot of current through one pin if the signal source could supply it.  Current density in a structure on silicon becomes the enemy in that situation.  In using our EVM in our lab, I usually am using a signal generator with SMA cables, so my source is inherently limited anyway.

    If I may oversimplify a bit, in general we are concerned about two things with the absolute max specifications.  One, we don't want a circuit to 'pop' which is not something I'd worry about in this case.  The other is current density through a circuit and its effect on long term reliability.  In the lab I don't worry about whether the signal is present to the EVM before power because I'll not be using this EVM all day every day for 10 years, which in normal usage is what I believe our minimum expected lifetime for a device is.    So if I *can* get a current limit from design, then that would be a limit that the designer can sign up for without failing design rules for long term reliability.  Violating a spec like this is an accumulative thing - the larger the violation, the longer the duration of the violation, and the frequency of occurrence of the violation all contribute to increased probability of eventual failure.  if we are talking about an event that happens on powerup a few times a day, for milliseconds at a time, then I would not be too concerned.  An event lasting many seconds, many times an hour - I'd be more concerned.

    If AC coupled such that the device could bias the signal up to VCM, then the VCM will also be zero while the device is not powered up, so the signal will swing about 0V.  Full scale is defined as 3V peak to peak differential, which is +/-0.75V around VCM on each pin of the differential inputs.  If the ESD diodes do kick on at exactly 0.3V, this leaves 0.45V max violation, with a relatively small duty cycle of conducting/nonconducting.   Still - I cannot put a number on how long you could put the device in this condition or what to limit the current to unless I can get guidance from design, which I will ask for.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Intellectual 275 points
    Hello Richard

    Thank you for getting back to me.

    Here are the answers to your questions which would hopefully make it easier to come to a solution:

    The typical operating amplitude is 0dBm (50R). I am not aware of the complete system design, but I would suspect that there is no signal present during the unpowered state (supplies at 0V). Certainly, the temporary overload condition would not happen during the unpowered state. We only need to consider the powered up case.

    The input is AC coupled so there is no DC offset (the only DC offset is the VCM implemented by the ADC itself).

    The input is as follows:
    a) a signal from a "source" is driven single-ended at 50R
    b) a 2:1 transformer converts this single-ended signal into a differential signal
    c) there is a 100R termination across the transformer secondary for impedance matching
    d) there are 10nF AC coupling capacitors, followed by 10R series resistors connecting the transformer secondary to the analog inputs of the ADC

    I hope that helps.

    Thanks again
    Gavin