Greetings.
I wanted to double check that my clock calculations are correct for the DAC3283:
What I need is I/Q (dual channel) which have an input sample rate of 80 MSPS each. Using DDR to send 2 bytes every clock cycle, but needing 2 clock cycles to send the entire I/Q frame, my data clock will be 160 MHz.
My DAC clock will be dependent on what kind of interpolation I would like:
1x interpolation: 160Mhz -> Output sample rate of 80 MSPS per channel
2x interpolation: 320MHz -> Output sample rate of 160 MSPS per channel
4x interpolation: 640Mhz -> Output sample rate of 320 MSPS per channel
Is this correct?
