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FPGA Firmware Example of How To Interface Altera FPGAs to High-Speed LVDS-Interface Data Converters TIDA-00069

Other Parts Discussed in Thread: ADS4249, ADS5474, TIDA-00069

Dear All

I have downloaded reference Verilog code for abouve mentioned subject, but its downloed in .qar . any body have reference code in zip ??? 

Thanking you in anticipation

  • Faseeh,

    The Altera design tool called Quartus uses files with a .qar extension. This is the project file. If we sent it zipped and you unzipped it, it would be the same file.

    Regards,

    Jim

  • Dear Jim
    Thanks , I opened reference file successfully . Do you have above reference code in VHDL
  • Hi,

    We just have the Verilog that was used in this project, not VHDL.

    Regards,

    Richard P.

  • what is the minimum magnitude of input signal required to produce a specified output signal for ADS4249.
  • Hi,

    Please elaborate.   What kind of specified output?   There is not minimum amplitude for the analog input signal for there to be an 'output'.   There always is an output.   With no input signal at all (sometimes called Idle Channel) there will be an output of mid-scale codes, with a few lsb's of Idle Channel noise.  

    Regards,

    Richard P.

  • Dear 

    Thank you for your response . 

    I have ordered ADS5474 and ADS4249. 

    My question is simple that what will be the minimum analog input signal (in db or Watt ) coming from Antenna or air for ADS5474 and ADS4249 to sense.

    will it able to sense -110dbm or lesser 

    Thanks 

  • Hi,

    That question is much too unbounded to answer simply.  But if you consider that the ADCs you are considering will have a datasheet SNR of maybe 72 to 74 dB depending on the input frequency, and a full scale input of about 2V, relating that that back to noise spectral density for our data converters we will find that we will have a noise spectral density of maybe -143 dBm/Hz or so.   So if you are digitizing the signal and take a deep enough capture of samples to do a long enough FFT to get the Hz/bin down to something low and then average many such captures to process the noise floor down to something very low then yes, you would begin to see your -110dBm signal stand out of the noise floor.   But for a single 32K point FFT such as presented in one of our datasheets notice that the noise floor of the FFT is down around -100 dBFS to -110 dBFS, with FS around +10 dBm, so no you would not see your signal stand out there.

    Regards,

    Richard P.

  • Thank you for your time. Will post in future if needed.

  • Dear

    Can you please suggest me any Xilinx IP core compatible with Altera Megafunction ALTLVDS_RX and ALTPLL. I am configuring ADS4249 with Xilinx VC 707 kit. After going through FPGA Firmware Example of How To Interface Altera FPGAs to High-Speed LVDS-Interface Data Converters TIDA-00069 , I need Xilinx IP Core for Altera megafunctions used in the example code.

    Best Regards

    FRK