How to synchronize multiple ADCs and FPGAs across JESD204B link

 i am learning how to use Jesd204 device , plan to design a 12 channel synchronous sampling system,made up of three boards,4 channel each.

Sampling rate = 480Msps, FPGA refclk = 120MHz, SYSREF = 7.5MHz

The reference input of the three boards is provided by the splitter with common 20MHz

I plan to use LMK04828,it is a complicate device,synchronization of multiple LMK04828 is critical. 

Hi Jim B

thanks for your reply
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1) The architecture used in that diagram does need the internal LMK04828 dividers to be initialized. The use of 0-delay feedback mode from the SYSREF output to the reference input ensures the SYSREF output of each LMK04828 will be phase aligned to the input reference (at F_SYSREF). To ensure the clocks for the FPGA are also aligned, the internal dividers must be reset/initialized. That can be done using either register writes alone or a combination of register writes and logic signal inputs to the SYNC input pin.
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SYSREF output of each LMK04828 is phase aligned to the input reference,--->DCLK output is phase aligned to the SYSREF,
--->since SYSREF is the lowest frequency,DCLK frequency is inter multiple of SYSREF,DCLK of multiple LMK04828 is phase aligned even each LMK04828 internal dividers are reset at difference instant.
the key is :DCLKs frequency must be 2^n integer multiple of SYSREF,right?

in the figure above,DCLK2 is phase aligned with SYSREF,DCLK3 is phase aligned with SYSREF,but DCLK2 and DCLK3 are not phase aligned.using register writes can not sync two LMK chips,even in 0-delay mode.

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2) To ensure consistent alignment of the 2 ADC+FPGA systems, the FPGA clocks should be phase aligned with SYSREF.
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both the refclk and coreclk(external) should be phase aligned with SYSREF?

thanks for your reply

device clock for ADC/DAC and reference clock for FPGA RX are phase aligned with SYSREF in each EVM-board,The deviceclock and reference clock of the two boards are aligned with each other,but SYSREF are not aligned with each other.

The sampling instant is the rising edge of the sampling clock,so i should get the same sampling data;

clocks are sync with SYSREF,so the link latency should  be the same;(each individual board looks exactly the same!)

 reference clock for FPGA are phase aligned,so sampling data can be buffered and captured by the same clock edge.I should see perfectly identical sample tracks, is it right?

SYSREF phase relationship between multi-boards seems to be irrelevant?

Hi min hu

The JESD204B IP from FPGA vendors all use the LMFC frame boundaries to align the captured data output from the de-serializer blocks and sent to the downstream logic.

Even if you wrote your own capture IP from scratch some of the data formats will not allow you to generalize the data capture to octet or sample boundaries. Some formats have added Tail bits at the end of each frame, or every second octet, etc.

See Tables 12 and 13 of the ADC12J4000 datasheet for examples.

So sometimes the data must be handled on a frame boundary perspective at minimum.

Best regards,

Jim B