ADS4245: ADC/FPGA LVDS interface

Rotem Sasporta

Part Number: ADS4245
Other Parts Discussed in Thread: LMK04000

Hi,

The ADS4245 will be connected to Altera FPGA in LVDS mode (similar to what you demonstrates in http://www.ti.com/lit/ug/slaa545/slaa545.pdf)

The FPGA (CycloneV E) LVDS transceiver are connected to A 2.5V bank.

Following is a simplified block diagram of our system:

My question is:

The ADC Input CLK Vid = 0.7V :

The FPGA Vod_max = 0.6V:

It seems like there is a mismatch between them..

Can you please check if the ADS4245 1.8V LVDS interface can be connected directly to Altera Cyclone V E 2.5V LVDS bank?

The ADS4245 will be connected to Altera FPGA in LVDS mode (similar to what you demonstrates in http://www.ti.com/lit/ug/slaa545/slaa545.pdf)

The FPGA (CycloneV E) LVDS transceiver are connected to A 2.5V bank.

Following is a simplified block diagram of our system:

My question is:

The ADC Input CLK Vid = 0.7V :

The FPGA Vod_max = 0.6V:

It seems like there is a mismatch between them..

Can you please check if the ADS4245 1.8V LVDS interface can be connected directly to Altera Cyclone V E 2.5V LVDS bank?

Please advise.

over 7 years ago

0 jim s over 7 years ago

TI__Guru* 91947 points

Rotem,

Are you trying to verify if the digital outputs (data and clock) of the ADC are compatible with the Altera 2.5V bank input? If so, the answer is yes. Why are you mentioning the ADC input clock Vid? Do you plan on driving this with the Altera device? Your block diagram is not visible. If so, this would probably work but is highly recommended not to do this as the jitter on this clock from the FPGA will dramatically reduce the performance of the ADC. Instead, the ADC should be clocked from a low jitter device such as a LMK04000 from TI.

Regards,

Jim

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ADS4245: ADC/FPGA LVDS interface