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ADC16V130: ADC16V130-jitter requirement

Part Number: ADC16V130

Hi,

  For our  Satellite modem Receiver design 

  Requirements are :
  SNR: 70db,
  IF (Fin) : 70 Mhz;

We are using  16 bit ADC16v130  in our design.

To meet the SNR of 70 db , clock jitter is calculated using this formula:

SNR =-20*log(2*pi*Fin*Jitter RMS);

from the above formula i could see  total Jitter RMS =  718 fs;

for ADC16v130 Aperture jitter : 80 fs (Datasheet);

Hence, external Clock  jitter = sqrt(total jitter 2RMS -Aperture jitter2) = 713 fs;

Clock scenario in our design :

 10 MHZ TCXO reference --> LMK00308 (clock buffer,10Mhz CMOS output) --> LMX2581 (fractional pll- output 392 Mhz)  --> lmk1801(divider buffer- output 98 Mhz) --> clock to ADC 98Mhz

As per Datasheet additive RMS jitter :

 LMK1801  : 50 fs (intg.BW  :12khz to 20 Mhz)
 LMX2581  :100 fs (intg. BW 100 Hz to 10 MHz)
 LMK00308 : 51 fs (intg.BW : 12khz to 20 Mhz)
 
for TCXO   based on the phase noise values mentioned :

 Phase Noise, 10.000MHz (dBc/Hz)
10Hz       -94
100Hz     -118
1kHz       -135
10kHz      -147
100kHz    -152

Based on these values RMS jitter comes out to be :  1.5ps (intg.BW 10HZ -20 MHZ)

Clock jitter to ADC : crystal jitter + lmk00308 + lmx2581+lmk1801 = 1.6ps , but the requirement is only 713fs

Is this the correct procedure in calculating the clock jitter ?
 
For ADC clock  :98 Mhz , what should be the intg.BW to be taken to calculate RMS jitter from Phase noise plot  seen in R&S analyzer ??

Is it  from 12khz to 20 Mhz  or 10 Hz to 20 MHZ ??

  • Naresh,

    We are looking into this.

    Regards,

    Jim

  • Hi,

    here some feedback. You are well on the way of a very thorough analysis. You also need to include the ADC thermal noise in your equation which is about 78.5dBFS.

    For target of 70dB SNR @ 70MHz IF and ADC aperture jitter of ~ 80fs I calculate about 730fs of max jitter. This is assume the SNR target is with a fullscale single tone signal. For modulated signal the SNR will improve as signal will be backed off from the ADC fullscale.

    Your integration limits for the jitter calculation may need to be adjusted. Does your application really need it to 10Hz? For example if your carrier bandwidth is 200kHz with a channel spacing of 50kHz then your min integration limit should be 150kHz assuming a single tone in the middle of the carrier and a very weak signal in the adjacent carrier. A single tone often times is used as a worst case interferer scenario.

    The far end integration limit can be set by several items:

    - bandpass filter on the clock input

    - ADC clock input rolloff (not the case for ADC16v130)

    - sampling window: in this case would be 2x the clock rate as noise is folding back. Often times the clock source noise rolls off with higher frequency offset

    the integration limits given in the clock device data sheets (eg 12k - 20M) come from an older telecom specification and are often used for comparison across different devices.