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ADS5409: ADS5409/ADS5400 Parameters

Intellectual 510 points

Replies: 8

Views: 683

Part Number: ADS5409

We have the following requirements in a Measurement system where we are considering usage of either ADS5409 or ADS5400:

1) 4mV – 1Vpk-pk differential input amplitude support (It is very important to detect the 4mV signal amplitude)

2) Sampling rate 900MSPS/1GSPS (The highest input signal frequency is seen to be ~ 400MHz)
3) Preferred output SDR/DDR LVDS
We have compared the ADS5400 and ADS5409 devices as below:
a) ADS5409 has a better SINAD at 400MHZ and gives ENOB of 9.8 bits. ADS5400 gives 9.4 bits.
b) ADA5409 selectable min FSR is 1.5V, while ADS5409 can be configured at 1V using VREF SEL. Based on this, effective resolution is 2.2mV for ADS5400 and 1.1mV for ADS5409.
c) With Auto-correction, ADS5409 has an offset error of +/- 1mV. ADS5400 is fixed to +/-2.5mV. INL figures are also better for ADS5409.
d) ADS5400 has a conversion latency of 7-8.5 Clock cycles, while ADS5409 has 50 cycles latency in auto correction mode.
Overall, based on what we would like to achieve, the ADS5409 looks suited. But we would like to check with TI if we are missing out on anything critical here that can make ADS5400 better suited.

Regards
Gaurav

8 Replies

  • Guru 68690 points

    Gaurav,

    We are looking into this.

    Regards,

    Jim

  • In reply to jim s:

    Thanks Jim, we appreciate an early response if possible. The design closure is waiting for the selection of this part.

    Regards

    Gaurav

  • Hi,

    Well, you've already compared the most obvious datasheet specification of the two device, such as SINAD and ENOB, as well as the full scale range and things like offset error and INL.

    But beyond that, I don't know what you mean by 'detect' when you say you need to detect the 4mV pk-pk amplitude signal. That is a vague term.  You've already considered the 12 bit resolution against the full scale range to be able to express the resolution in terms of mV, as well as using the effective resolution (ENOB) to express the resolution in terms of mV.  (1.1mV for the ADS5409 or 2.2mV for the ADS5400)    But that is just the resolution of a single sample.  if you take a capture of samples (such as 65536 samples) and do an FFT on the samples, then the noise floor may be down around -100dB from full scale, and a larger FFT would push that noise floor down more, such that a 4mV signal would stand out clearly from the noise floor.  or if multiple such captures were averaged then the overall level of the noise floor doesn't change but smoothes out making the 4mV signal stand out more clearly.  you mention that your 4mV signal would be no higher than 400MHz, so it sounds like a repetitive signal that could be captured and processed, compared to something like a single pulse. 

    I would suggest evaluating the two devices with your signal with the ADC EVM and the TSW1400 capture card with HSDCPro, or at least starting with the device you think is best suited.   The ADS5400 has a little poorer specs but a little higher sample rate, but the LVDS bus timing into your FPGA would be easier using the dual-but output format.  The ADS5409 is an interleaved device such that there really are two internal ADCs per channel to achieve the rated sample rate, and that gives rise to interleaving mismatches that show up as spurs in the output spectrum which could be mistaken for your signal if the autocorrection algorithm doesn't work as well as you might need it to.  In the ADS5409 EVM User Guide figure8 there is an example FFT of an input signal at 185MHz.  http://www.ti.com/lit/ug/slau450/slau450.pdf   In that FFT, you can see an unlabeled spur at about 215MHz between the 185M and the 3rd harmonic.  That is an artifact of the interleaving mismatches.  But as the artifact shows up at a location of Fs/2 - Fin (that is, at the Nyquist minus the input freq) and is therefore a function of the input tone, if the input tone were very small like your 4mV signal then the artifact also would be that much smaller.  So I don't think it would hurt you.   But I would encourage you to evaluate the EVM into the TSW1400 capture card, or the cheaper TSW1405 capture card.

    Regards,

    Richard P.

    Regards,

    Richard P.

  • In reply to Richard Prentice:

    Thanks Richard.

    Sorry if I could not present it right. The signal is not repetitive, but a single analog pulse of around 20ns width, with a 2.5-3ns peak period that is important to detect. The signal can have a voltage ranging from 4mV to 1V pk-pk.

    So I am not sure how much averaging can help really. Please let me know if you have any further inputs.

    Regards
    Gaurav
  • In reply to Gaurav Agrawal1:

    Hi Richard,

    Please see if you can provide any further details as per my last mail.

    Regards

    Gaurav

  • In reply to Gaurav Agrawal1:

    Hi,

    ah, I was wondering if the signal was maybe a tone since there was mention of it being no more than about 400MHz, but being a pulse I can see that you do need to just be able to grab it and see it.   And that with a higher sample rate you would be able to see more samples of it.   Hmm, in the comparison of the ADS5400 and ADS5409, one drawback to the ADS5409 would be that it is a 2 channel device where you would only need one channel.   But another way to get better SNR and ENOB would be to use more ADCs in parallel sampling the same signal at the same time and average the samples.  For every doubling of the number of ADCs you would get a nominal improvement of 3dB of SNR by averaging the results across the ADCs, assuming the noise in each ADC is uncorrelated.   That would be an expensive way of getting better SNR if the best ADCs you can find at these higher sample rates are only 12 bits in resolution.   But two 12bit ADCs in parallel averaged would look like a 12.5bit ADC, and 4 in parallel would look like a 13bit ADC, etc.   Another option in the ADS5409 is the decimation filter.  The decimation filter in the ADS5409 cuts in half the number of samples from the ADC to your FPGA, bringing the effective sample rate down to 450Msps, but for each decimation by two there is a nominal 3dB gain in SNR.  A decimation filter on a faster ADC essentially provides the same kind of SNR processing gain that doubling number of ADCs would do.  But for a 900Msps ADC, the decimation filter may be enough to still capture a number of samples of a 20ns wide pulse, but with better effective SNR/ENOB. 

    Also recently released is the ADS54J60 which can supply 16bit samples a 1Gsps, and that also has 2x or 4x decimation filters to cut down the bandwidth needed into the FPGA while providing the resulting processing boost in SNR.   But that device uses the JESD204b sample format, requiring an FPGA capable of receiving 2 to 4 lanes of high speed serial data per channel of ADC.  It is much more involved than just an LVDS data bus.  Trying to get more resolution at higher sample rates eventually pushes beyond what it feasible with LVDS and the JESD204b is the next step for more data bandwidth.   If the ADS5409 with or without the decimation filter does the job for you, then that would be simpler than something like the ADS54J60. 

    Regards,

    Richard P.

  • In reply to Richard Prentice:

    Thanks Richard, we will go ahead with ADS5409. Jesd204b isn't really an option now as the IP needs to be bought.

    So can we also use the two channels of ADS5409 in parallel on the input pulse for a better resolution? Our signal source is 50 ohm, so we need to check out the line interface circuitry once.

    Regards

    Gaurav

  • In reply to Gaurav Agrawal1:

    Hi,

    I made some inquiries regarding our experience with using two or more parallel ADCs with the samples averaged for better SNR.  Recall I pointed out the assumption that the noise in the two ADCs must be uncorrelated for the SNR improvement to be a full 3dB, and with two channels in one device this may not be a completely accurate assumption.   Thermal noise will be uncorrelated,  while some clock noise will be correlated.    On a different device, we saw about 2.5dB improvement in SNR by averaging two channels, compared to the maximum possible 3dB. 

    But care must be take in the routing of the signal to the two analog inputs that the signal gets to the two inputs without routing skew and that any additional loading doesn't degrade the performance by more than what you look to gain by the averaging.  But it is common to use two or four ADCs in parallel to interleave the samples to a higher effective data rate rather than averaging for higher SNR, and the same routing and loading issues are present in those applications as well and can be overcome.

    Regards,

    Richard P.

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