**Part Number:** ADS61B29

Hi,

We want to measure the noise floor of my ADC ADS61B29 (12 bit @ 50MSPS). For that we terminated the input of ADC and captured the digital samples using FPGA. We are having some doubts in the calculation. This is split into 2 experiments.

Experiment setup details :

Sampling freq : 50MHz.

Two's complement enabled in ADC : YES.

Tool used : Wavevision 5.0.4.764

FFT windowing used : Flat-top with reset value of bins to omit.

- We captured the samples (file attached : 12bit.txt) 12 bit resolution at 50MHz sampling freq, twos complement enabled. Plotted in wavevision. Observed average noise of -100dBFS which is -90dBm (which is from 10 - 100 , is this calculation correct?). Removing the FFT processing for 2048 samples which is 30.1dB, the noise floor is
**60dBm.**Which is fine since the ADC SNR can be upto 64dBm (since 10dBm being the full scale). Is this calculation is correct? Am I missing something here? - The samples of the above capture is divided by two (taking only MS 11 bits) and plotted in wavevision. (file :11bit.txt ). Observed noise floor -111.62dBFS => -101.62dBm, removing processing gain => -71.52dBm. This value is beyond the value that can be represented using this 11bit ADC, right?

I'm sure that I'm missing some fundamentals. It will be very helpful if anyone can tell me in which part I went wrong. How to correct it?

Is the calculation is correct : ADS61B29 full scale input is 10dBm. SNR = 6.02N+1.72dB = 74dB.. But since 10dBm being full scale, 64dBm is the SNR.

Thanks in advance.