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Part Number: ADS61B29
We want to measure the noise floor of my ADC ADS61B29 (12 bit @ 50MSPS). For that we terminated the input of ADC and captured the digital samples using FPGA. We are having some doubts in the calculation. This is split into 2 experiments.
Experiment setup details :
Sampling freq : 50MHz.
Two's complement enabled in ADC : YES.
Tool used : Wavevision 220.127.116.114
FFT windowing used : Flat-top with reset value of bins to omit.
I'm sure that I'm missing some fundamentals. It will be very helpful if anyone can tell me in which part I went wrong. How to correct it?
Is the calculation is correct : ADS61B29 full scale input is 10dBm. SNR = 6.02N+1.72dB = 74dB.. But since 10dBm being full scale, 64dBm is the SNR.
Thanks in advance.
the .txt files attached don't seem to be the complete sample, I just see 2048 '1's or '0's. it would appear that each sample was rounded up to 1 or down to 0, or maybe most of the bits were just truncated. so I can't do anything with the files attached.
I am not familiar with Wavevision, as the usual tool for evaluating the ADS61B29 EVM is the TSW1400 capture card into the HSDCPro GUI. If you have a capture buffer of data from your FPGA then I would recommend importing that into HSDCPro rather than Wavevision.
But something does seem to be wrong if you took a 12bit sample and saw one noise floor, and then dropped the lsb of the sample to keep an 11bit sample and saw a *lower* noise floor. it should have gone the other way to a higher, (that is, poorer) noise floor.
The 10dBm being full scale presumes a 10dBm into a 50 ohm load, as the ADC full scale is in voltage, not power. But 10dBm into a 50 ohm load *is* 2V peak to peak, which is our full scale, but that doesn't necessarily relate to SNR. The equation you quote to SNR is the theoretical max SNR as a function of resolution. The actual SNR will be further degraded by clock jitter, and there is another equation that relates SNR to clock jitter. And since an ADC will have some specified internal aperture jitter, that also sets the SNR limit for a device.
But back to your data captures, I would suggest you check the format of the data and import them if you can into HSDCPro. Once imported, you could view the samples in the time domain in a logic-analyzer style display to see that the msb is where it belongs, etc. you can view the samples as codes vs time, to see that the samples are centered around mid-scale and have a min and max value that is reasonable, or see what the idle channel noise is in terms of lsb's. and then view the FFT. If need be, we may have a person available here that could address questions specific to Wavevision, although that tool is no longer in use.
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In reply to Richard Prentice:
Thanks for the reply.
The samples captured corresponds to a terminated input. i.e., ADC input is terminated using a 50 ohm termination. So the '1's and '0' s in the samples actually corresponds to the noise.
I don't think this is tool dependent. Because I used MATLAB code for this FFT plotting provided at e2e.ti.com/.../526257
And as you agree there is something wrong when we take 11bits. That is my concern
So my calculation are correct with respect to dBFS to dBm. i.e 0dBFS is 10dBm in our case.
Wavevision also similar to HSDCPro. But we always use wavevision in our company.
As you agree, the actual SNR will be further degraded because of other reasons. But I'm seeing much better SNR in some cases and especially If I take 11bit. As you agree, theoretical SNR will be = 6.02*12 + 1.7 = 74 , if full scale is 0dBm.
I've only one technical doc as reference : http://www.analog.com/media/en/training-seminars/tutorials/MT-001.pdf
please note that the ENOB went to 13bits even though I'm using 11bits.. Same thing is plotted using MATLAB :
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