Hi,
I'm designing a 4-20mA current loop receiver and I am interfacing it to a Beaglebone Black (Sitara AM3358BZCZ100). The 4-20mA data will run at 19.2kbps. I have to run the ADC at a rate of 307.2KCPS to sample the data with a 16 X oversampling. The signal chain that I have is the following. 16-bit ADC -> SPI -> Isolator -> CPLD -> UART -> Sitara AM3358BZCZ100 The SPI bus is targeted to run at 4.915MHz. I need to have the CPLD in the chain to sample the ADC data. For reliable data communication, usually it is recommended to be oversampling the input by X8 or X16. The Sitara AM3358BZCZ100 cannot do this function in it's serial controller, and the software certainly cannot sample the SPI data in real time. I have a CPLD in the path that does the X 16 sampling and converts the data into UART format, at a data rate of 19.2Kbps which the Sitara AM3358BZCZ100 processor can buffer and process.
According to the reference manual for TIDA-00123 www.ti.com/.../tidu191.pdf , a first pass reading of figure 5 and figure 6, would indicate that the data from the ADC goes straight into the M4-Cortex processor where it is buffered and stored. Don't you have to over-sample the ADC data? Please clarify how the data goes from the ADC into a format that the software can buffer and process
Is it possible that I do not need to over-sample the ADC data? Please clarify.
Thank you very much for your help.
Jeff Cohen
Hytorc Inc. Mawah, NJ