ADS5400EVM interfacing with Xilinx KC705 through a FMC-ADC-ADAPTER

Hi,

no, not a problem.  You just need to be aware of it and account for it in your FPGA code.  I've mentioned elsewhere on a number of E2E postings that when we would have our layout person create the layout for the circuit board that we would usually direct the LVDS to layout directly to the connector in the cleanest manner possible and to avoid vias through the board.  If that meant that the polarity of the LVDS ended up inverted at the connector compared to other EVMs, then we would just account for that inversion in the FPGA code.   It might be clock that would be inverted, or all the data lines, or both or none.  The one thing we would not do would be to have some of the data lines inverted and others not inverted - we did not allow that.  If clock is inverted and you do not account for it in the FPGA then the results would be obviously wrong as samples would get swapped or even and odd bits swapped.   If data were inverted and you did not account for it in the FPGA then the results may not be immediately apparent when looking at a single tone sine wave -  an inverted sine wave still looks like a sine wave.  but a known test pattern would show the error quickly.

Regards,

Richard P.