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AFE7070 Dual input clock(00)

Guru 10750 points
Other Parts Discussed in Thread: AFE7070

Hi,

I want to work with the AFE7070 in "Dual input clock(00)" mode. I have configured register0 value to 0xB6 or 0xB4, and there is no RF output, When I change the "data_clk_sel" to '1', it start work( their is output RF),even if I disconnect the CLK_IO signal from the input. The CLK_IO signa to the AFE7070 looks OK. Currently, I use an abnormal configuration since the value of register0 is 0xBE, anything I can do to have thi smode working?

Many Thanks,

HRi

  • Hello HRi,

    In Dual input clcok mode Config0 should be set to 0xB2 value. Table 3 on page 19 of the datasheet show the correct resister settings. The fifo should be enabled. Is your CLK_IO frequency locked with DACCLK?

    Regards,

    Neeraj Gill

  • Hello Neeraj

    I am HRi college. How can I know that  CLK_IO signal is locked with DACCLK. I'm my implementation, they are from the same source. Do I have any indication that they are locked?

    In page 28, figure 29 its described that the "IQ Identification" can be either IQ_Flag or SYNC_SLEEP. I think its a mistake. It can be IO_FLAG only. Is it a mistake or IO_FLAG is not required? In my implementation, I their is no IQ_FLAG signal.

    Please look at the next figure.


    Ofer
  • Hi Ofer,

    If your DACCLK and CLK_IO are coming from the same source then they should be frequency locked.

    IQ_FLAG is required to identify I and Q data(mistake in the datasheet). As mentioned in the datasheet. The IQ_FLAG signal can either be a repetitive high/low signal or a single event that is used to reset the clock divider phase and identify the I sample.

    Regards,

    Neeraj Gill