Other Parts Discussed in Thread: CC2640
Hi,
One of my customers intend to use the ADS8320 in combination with a CC2640 and connect it to the SPI interface.
Sample frequency has to be 100KHz.
The timing diagram of the ADS8320 shows that you need to clock out 24 cycles
The ADS8320 timing diagram shows that the CS line is going high before the last of the 24 clock pulses, which is not what a standard SPI port will do.
Is it possible to have the SPI shift out 24 clock cycles (3 consecutive byte write operations), puts its CS line high and reads in 24 bits.
The meaningfull databits are read in starting at the rising edge of the 7th. clock pulse.
CS goes high for a short period of time after the 24 clock cycles and then the next sequence of 24 clock cycles starts.
From the ADS8320 datasheet I understand that if the CS line is kept low for the full 24 clock cycles the next conversion is already started whilst the idea is to start the next conversion when the CS line goes down again and the SPI sends out the next sequence of 24 clock pulses.
Can you confirm that this will work as well?
