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ADS5240: ADS5240 low sample rate operation.

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Part Number: ADS5240

Hi:

Datasheet show sample rate is from 20~40 MSPS, If we want to use lower 20 MSPS, for instance 1MSPS, does it have any bad effect?

Thanks

Jimmy

1 Reply

  • Hi,

    the ADS5240 has a serialized output to output the 12 bits of sample data onto a single LVDS pair at 12 times the rate of the sample clock, and to do that the ADS5240 has to take the sample clock and multiply it up by a factor of six to generate the DDR bit clock for the serial output.  This requires a PLL to take the sample clock and multiply it up to make the LVDS bit clock.   PLLs will commonly have a maximum and a minimum for the clock frequency that they can lock on to, and a factor of 2 to 1 from maximum to minimum is not uncommon.   A sample clock of 1MHz would be so much below the minimum sample rate that the PLL would probably fail to be able to lock on to that clock at all.    Under nominal conditions the actual range of frequency over which the PLL might be seen to operate might be wider than the datasheet limits, but over the range of temperature and voltage these limits are what the device is guaranteed to support, and these are the limits to which the device is tested in production.   We cannot guarantee operation outside of the min and max limits.

    Regards,

    Richard P.

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