Hello,
I'm debugging a problem and need a little help understanding the ADS8344 SPI bus. Figure 4 (page 13 of the datasheet), indicates two things:
- DCLK must be low during the falling edge of the chip-select (CS#) event.
- DCLK must remain low for a period of tCSS = 100ns before the first DCLK rising edge.
My application meets criteria 2, however, in some cases, criteria 1 is not met. A falling edge of DCLK sometimes occurs 10-50ns after the falling edge of CS#.
What potential problems could there be in this case?
Don