I am interested in working with the ADS4145 ADC. I had a few questions on this part.
1. The data sheet lists 20MHz as the lowest clock frequency that this ADC can work with. Our application needs 16.5MHz ADC clock speeds. Is this OK ? How low can we go in sampling speed before the ADC performance goes bad ?
2. We plan to use multiple ADCs in our system and all sampling clocks reaching the ADC will be synchronized. Will all these ADCs be synchronized with this architecture ? Are there any reasons for phase ambiguity in the data due to the ADC architecture ?
3. To enable DC offset correction, is the register write sequence to set EN OFFSET CORR to 1 and then program the offset time constant in register CF ? or is it the reverse order ?
4. I plan to use the ADS4145EVM circuits for my application. Any reasons why the DC offset at the input could exceed +-10mV ? I am just worried if the input DC offset goes over the correction capability of the ADC.
Thanks,
AB