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ADS54J60: ADS54J60：Test mode setup

user4632994
Prodigy 90 points
Part Number: ADS54J60


Hi，all

        According to the ADS54J60 datasheet, There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J60
supports There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J60
supports a clock output, encoded, and a PRBS (215 – 1) pattern. These test patterns can be enabled via an SPI
register write and are located in the JESD digital page of the JESD bank.(215 – 1) pattern. These test patterns can be enabled via an SPI
register write and are located in the JESD digital page of the JESD bank.

        I want to know which register to be config that  ADS54J60 can work in the test mode(a clock output, encoded, and a PRBS (215 – 1) pattern)  ?

  • 0
    TI__Guru* 91947 points

    User,

    In the JESD Digital Page 0x6900, register 0 bit 4 is used to enable the long transport layer test mode per section 5.1.6.3 of the JESD standard. In the same page, register 2 bits 7-5 allow for several other test modes to be enables per section 5.1.6.3 of the standard.

    Regards,

    Jim