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ADS61B29 - shifting clokout

Calum Mackinnon
Genius 4155 points
Other Parts Discussed in Thread: ADS61B29

 I have the following question from a customer

"See page 21 of the ADS61B29 data sheet. When the CLKOUT position is adjusted via serial register 0x44 and shifted by +/- (4/26)Ts, is this shift relative to the default position or the data transition?"

Shifting the clock is typically from the default position but  the datasheet doesn't explicitly say.

Cheers

Calum  

  • 0
    TI__Mastermind 29220 points

    Hi,

    When the data sheet refers to the clock edge position being shifted by + (4/26)Ts or - (4/26)Ts it is relative to the default position of the clock.   Ts is the period of the sample clock, and the timing section of the data sheet lists guaranteed setup and hold times for data relative to the CLKOUT for the default clock position, and from that point the clock edges may be shifted by - (4/26)Ts or by + (4/26)Ts.   Or the clock edges may be aligned with the data bit transitions, which is also known as source synchronous clocking.   One or another of these options may be more useful than others for a particular FPGA input circuit.

    Regards,

    Richard P.