ADC08200: ADC08200

Hi Svetlana

Due to the lack of a dedicated output Data Clock, and the relatively large output Delay and Hold times (and min/max variation of those times) for Data with respect to the input Clock, it can be somewhat challenging to reliably capture data from the ADC08200. For this reason the ADC08B200 is an alternative device, with Data Clock, that should be considered.

The best configuration is to utilize a capture FPGA that can adjust the Data strobe instant with respect to the ADC input Clock. The delay can be swept over a range and the points of data instability found, then the delay set to provide maximum capture timing margin. Since there is no data test pattern available, this method requires some knowledge of the input signal, ideally setting the signal at midscale to give data values near the 7Fh, 80h transition point.

I hope this is helpful.

Best regards,

Jim B

Hello Jim,

We already have a board with the ADC08200 device.

We have an issue with our board, once in a while we have a bad sample.

I would like to make sure that we are clear with the timing specification of the ADC08200 device.

What is the minimum tOH (see attached drawing)?

Is it 0nsec or 1.9nsec?

Thank you,

Svetlana.

ADC08200_timing.docx

Hi Svetlana

This is a fairly old device, and I don't have a lot of information available beyond what is found in the datasheet. Because of that I can't provide any guidance regarding tOH min. However here is some information I found from a former colleague on this same topic:

"The only difference between Tod and Toh is that Toh is measured at the 10%/90% points of the Dout waveform while Tod is measured at the Vdr/2 point. (This is now shown in Figure 2)

Otherwise they are both trying to represent the same Clk-to-Data Delay. We show Toh in the datasheet only to give an additional guideline. We only have limited data on the Toh - and this is why only a typical value is specified. Over temperature min/max limits can only be specified for the Tod where we have much better data.

For your analysis we believe that Tod-min would serve the same function as Toh - as long as you account for the rise and fall times of the Data and Clock signals appropriately. In our testing we have seen the Data output's rise time (Tr) to be about 2 nsec and the fall time (Tf) to be about 3 nsec (10%-to-90%). It must be stressed that these Tr/Tf numbers are based on a small sample of lab observations and by no means a guaranteed limit."

I hope this is helpful.

Best regards,

Jim B

Hi Jim,

To make sure we understood correctly, can you please add a drawing of the sampling window for a 6.25nsec period?

Thank you,

Svetlana.

Hi Svetlana

Here is a drawing showing the output data timing based on the min/max tOD specifications and 160 MHz clock rate.

ADC08200 Data Timing 160 MHz Clock.pdf

Best regards,

Jim B