• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 46 subscribers
  • Views 2581 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS7953: ADS7953 spi issue

user1359349
Intellectual 450 points
Part Number: ADS7953


hello

    we used the ADS7953 for my design,as the  figure 1,

now the chip working is ok ,and i can read the right value,but when i test the signal,i have found the SDI ,SCL,CS is ok,the SDO maybe not quite right ,

please refer the figure 2:the red line marked maybe have problem,why is there a another signal here,and the rising edge was so slow.please refer the figure 3:

if we disconnect with cpu,the ADS7953 output signal also not right,please see figure 4,when i disconnect with cpu ，the falling edge of the signal become very slow( when connect with cpu ,the rising edge is slow)

can you tell me,why has the happend? and is this normal or not?

thanks you very much.

fugure 1

figure 2

figure 3

figure 4

  • 0
    TI__Mastermind 21685 points

    Hello,

    >>>>>please refer the figure 2:the red line marked maybe have problem,why is there a another signal here,and the rising edge was so slow.please refer the figure 3:

    Please double check ADS7953 connections to AVR: check ADS7953 SDI is connected to AVR-MOSI and SDO is connected AVR-MISO. Otherwise, there’s a conflict between master write and slave write. Schematic indicates SDO is connected to AVR_SDO. AVR_SDO could be AVR SPI block working as a slave and sending out data. This can conflict with ADS7953 sending out data on SDO and make you see two signals as in figure 2.

    Also, make sure the ADS7953 SDO trace is short. Long traces mean high capacitive loads. Also, if you are connecting by fly wire ADS7953 SDO to AVR MISO then keep it short. By the way, please note SDO goes to tristate condition on the 16-th falling edge of SCLK. This might be what you are seeing on figure 4. What’s the clock freq you are using? Long SDO wire length and high clock freq would not work well.

    Thanks,

    Vishy

  • 0 in reply to Vishy Viswanathan
    Intellectual 450 points

    hello Vishy

      thanks for your advise,according your advise,i have doulbe checked my schematic,maybe the software have already upgraded,when i test it  again,the problem what i have mentioned last time,now is normal.

     thank you very much.

  • 0 in reply to user1359349
    TI__Mastermind 21685 points
    Thanks a lot for your update on this.
    Regards,
    Vishy