ADS1296: Read back 3 channels at 32ksps with spi clk = 4MHz

Hi Eduardo,

It's easier to think of this in time rather than frequency. First and foremost, you won't be able to skip CH1 in the ADS1296 configuration you describe above. You can neglect CH5 and CH6, but CH1 will still be present in the output data packet. At 32 kSPS, you'll have BUSY transition every 31.25 uS. To read the STATUS plus 4 channels, that's 120 bits. At 4 MHz, that's 250 nS * 120 bits or 30 uS.

In theory you'll have time to read all the data, but in practice you have to factor in whatever overhead your uC needs to process the interrupt, read and then store/process the data. The remaining 1.25 uS sounds a bit short to me - so, you can use CH1 and skip over CH3-5 to gain some time, or you can speed up the SPI clock to get data out of the device faster. Either option should give you an easier time collecting data from the ADS1296.

Tom,

Thanks for clarifying that I cannot skip CH1 since they are positioned immediately after the status bits in the frame order.  So first of all,I would change my hardware connections to only use CH1, CH2, and CH3 so that I would subsequently read back:  STAT...CH1...CH2...CH3 (total of 96 bits).  As mentioned earlier, I would like to keep the SPI clock frequency at 4 MHz(250ns), and sampling rate at 32ksps(31.25us), so it would take 24us (250ns * 96 bits) to clock out those bits and leave me with 7.25us (31.25us - 24us) to process the interrupt.  If 7.25us is not sufficient time to process the interrupt, at that point, I would need to either: a) skip more channels or, b)increase my spi clock frequency

Are my calculations correct and do they line up with your response? 

By not clocking out all the available bits before the next DRDY signal is possible as I proposed with no data corruption?  I was concerned that if all bits were not clocked out, some unexpected behavior might occur that causes data corruption.

Best Regards,

-E