Hi all,
When the sampling rate is 180Msps and this is no signal input , there is some DC offset level without offset correction as below.
When increasing the input signal level of 140 MHz, a phenomenon in which the spectrum level at 0 Hz increases separately from the signal appearing at about the original 40 MHz was observed.
Why does this happen?
I think the offset level is the almost constant, isn't it?
And when I want to reduce the this DC offset, Is it correct to set the registers as follows?
Reg 0x3D = 0x20
Reg 0x42=0x08
Reg 0xCF=0x00
After completing the offset correction, for freezing the offset pedestal, Reg 0xCF is set to 0x80.
Is it correct?
Regards,
Toshi