• State Resolved
  • Locked Locked
  • Replies 10 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 1825 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS7867: The difference of tc(sclk) between high VDD and Low VDD

ttd
Mastermind 7660 points
Part Number: ADS7867
Other Parts Discussed in Thread: ADS7041

Dear Technical Support Team,

Why does ADS7867 have the difference of tc(sclk) between high VDD and Low VDD?

Does ADS7867 have unusual  architecture?

Datasheet shows that the higher VDD is, the lower tc(sclk) is. 

Our customer'd like to use much larger than 6.7us with 3V , if possible.

In other word , more slower frequency(Hz) than datasheet spec of tc(sclk).

Typical ADC doesn't have maximum tc(sclk) spec, but this device have them and the limitation depending on VDD. 

Best Regards,

ttd

  • 0
    TI__Expert 3175 points
    Hi ttd,

    I am looking into this and will get back to you soon.
  • 0 in reply to Evan Sawyer
    Mastermind 7660 points
    Hi Evan Sawyer,

    Thank you for your reply.
    I'm looking forward to a response about this question.
    If possible , I'm happy to be able to resolve it early next week before New Year holidays.

    Best Regards,
    ttd
  • 0 in reply to ttd
    TI__Expert 3175 points
    Hi ttd,

    The speed is limited based on the parameters we use to test the device to ensure datasheet performance.

    If a lower throughput is required, I would recommend that your customer considers the ADS7041 which does not have this same speed limitation.
  • 0 in reply to Evan Sawyer
    Mastermind 7660 points

    Hi Evan Sawyer,

    Thank you for your reply.
    How come it that the speed is limited?
    For example, is there the limitation to keep the accuracy on datasheet like gain error?

    ADS7041 seems to be much easier to use sclk than ADS7867.

    Thank you for your suggestion.

    Best Regards,
    ttd

  • 0 in reply to ttd
    TI__Expert 3175 points
    Hi ttd,

    The ADS7867 is a typical SAR, but its digital circuitry is designed such that the ADC releases the SDO line (tri-states) after the final bit is provided. The time between the falling edge of the clock and the release of the SDO line has a fixed min and max value.

    I recommend looking at Figure 1 and the "Disable time" specification on page 9 of the datasheet to better understand.
  • 0 in reply to Evan Sawyer
    Mastermind 7660 points

    Hi Evan Sawyer,

    Thank you for your reply.
    Why are min and max value of "tDIS(EOC-SDOZ): Disable time" related to max 6.7μs"tc(sclk): Cycle time" ?
    I didn't understand these relationship.

    I'd like to know what happens when tc(sclk) is over max 6.7μs.

    I guess that leak current of sample & hold circuit with 3V is larger than leak current of low VDD, so sclk can't be slow with 3V VDD.

    Best Regards,
    ttd

  • 0 in reply to ttd
    TI__Expert 3175 points
    Hi ttd,

    I have removed my previous post, because after discussing this device with several colleagues I have found that the datasheet uses the specifications 'tc(sclk)' and 'tsclk' interchangeably which is misleading.

    To answer your original question, yes you can use this device to sample at a slower rate than 6.7 us (which equates to about 149 kSPS). In the timing requirements table the tc(sclk) is shown to be the period of the SCLK, but this is not actually the case. As such, I recommend the following:

    1) To calculate the full cycle time (tcycle), I recommend using the equation on page 17 of the datasheet, treating tc(sclk) as the period of your clock (SCLK)

    2) Please use an SCLK between 10 kHz and 3.4 MHz (assuming the supply is above 2.5V).

    If the SCLK is too low, then the charge on the sample and hold cap will deplete enough that the results will be inaccurate.
  • 0 in reply to Evan Sawyer
    Mastermind 7660 points

    Hi Evan Sawyer,

    Thank you for your reply.
    I was relieved to hear that user can use SCLK between 10 kHz and 3.4 MHz above 2.5V without performance degradation.
    It makes customer's development easy.

    You commented that the datasheet uses the specifications 'tc(sclk): μs' and 'frequency of sclk: Hz' interchangeably which is misleading.
    Do you have a plan to fix datasheet?

    Best Regards,
    ttd

  • 0 in reply to ttd
    TI__Expert 3175 points
    Hi ttd,

    We do plan to clarify the datasheet specifications as soon as possible, but if you have any further questions before the datasheet is updated please feel free to post them here.
  • 0 in reply to Evan Sawyer
    Mastermind 7660 points
    Hi Evan Sawyer,

    I don't have more questions so far.
    I'm looking forward to revising the version of datasheet.

    Thank you for your cooperation.

    Best Regards,
    ttd