• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 935 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC5674EVM: Attempting to generate a sawtooth wave with an Artix-7 FPGA

Toby Jones
Prodigy 30 points
Part Number: DAC5674EVM

Hi,

As stated in the title I'm attempting to generate a sawtooth wave with an Artix-7 FPGA.  I'm driving the DAC with a single-ended clock, and have followed the instructions for the single-ended clock configuration in the module's datasheet.  Unfortunately, I'm not seeing anything on the output pins.  I've verified that the data and clock from the FPGA are correct, as is the PLLLOCK indicator from the chip.  I'm hoping to talk to an engineer so that we can get this sorted out.  

Thanks a bunch,

Toby Jones

  • 0
    TI__Mastermind 20541 points
    Hi Toby,

    we are looking at your question and will get back to you soon.

    Regards,
    Neeraj
  • 0
    Prodigy 30 points

    Hello all,

    I've returned to this post to add some additional information.  Attached are some oscilloscope screen grabs, the first being the external clock signal and the second being the PLLLOCK signal.  I've also attached a spreadsheet where I tested each pin status on the DAC chip and tested them against my assumptions.  Maybe someone can identify an error in my configuration on the bench?

    Thank you very much,

    Toby Jones

    Images:

    Spreadsheet:

    Terminal Functions
    Terminal Name Terminal Number I/O Description Assumption Correct?
    AGND 37, 41, 44 I Analog ground return GND Yes
    AVDD 45, 46 I Analog supply voltage 3v3 Yes
    BIASJ 40 O Full-scale output current bias 1v2 Yes
    CLK 29 I External clock input 1kHz square Yes
    CLKC 30 I Complementary external clock input HIGH Yes
    CLKGND 31 I Ground return for internal clock buffer GND Yes
    CLKVDD 32 I Internal clock buffer supply voltage 3v3 Yes
    D[13..0] 3..16 I Data bits 0 through 13
    D13 is most significant data bit (MSB)
    D0 is least significant data bit (LSB)
    DIV[1..0] 27,28 I PLL prescaler divide ratio settings LOW, LOW Yes
    DGND 1,2,19,24 I Digital ground return GND Yes
    DVDD 21,47,48 I Digital supply voltage 1v8 Yes
    EXTIO 39 O Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).
    Used as internal reference output when EXTLO = AGND, requires a 0.1-uF decoupling capacitor to AGND
    when used as reference output.    		 1v2 Yes
    EXTLO 38 I For internal reference connect to AGND.  Connect to AVDD to disable the internal reference. GND Yes
    HP1 17 I Filter 1 high-pass setting.  Active high. LOW Yes
    HP2 18 I Filter 2 high-pass setting.  Active high. LOW Yes
    IOGND 20 I Input digital ground return GND Yes
    IODVDD 22 I Input digital supply voltage 1v8 Yes
    IOUT1 43 O DAC current output.  Full scale when all input bits are set to 1 Output
    Waveform    		 No
    IOUT2 42 O DAC complementary current output.  Full scale when all input bits are 0 !Output
    Waveform    		 No
    LPF 35 I PLL loop filter connection LOW Yes
    PLLGND 33 I Ground return for internal PLL GND Yes
    PLLLOCK 25 O PLL lock status bit.  PLL is locked to input clock when high.  Provides output clock equal to the data rate
    when the PLL is disabled.    		 Clk/2 Yes
    PLLVDD 34 I Internal PLL supply voltage.  Connect to PLLGND to disable PLL clock multiplier. 3v3 Yes
    RESET 26 I Reset internal registers.  Active high LOW Yes
    SLEEP 36 I Asynchronous hardware power-down input.  Active high.  Internally pull down. LOW Yes
    X4 23 I 4x interpolation mode.  Active high.  Filter 1 is bypassed when connected to DGND. LOW Yes
  • 0 in reply to Toby Jones
    TI__Mastermind 20541 points
    Hi,

    Can you please tell what is your clock rate datarate and what interpolaction mode you are using?

    Regards,
    Neeraj
  • 0 in reply to Neeraj Gill
    Prodigy 30 points

    No problem,

    My clock rate is 1kHz, the datarate is ~340Hz, and the interpolation mode being used is 2x interpolation.

    Thank you,

    Toby

  • 0 in reply to Toby Jones
    TI__Mastermind 20541 points
    Hi Toby,

    The first thing is want to mention is the clock rate = interpolation X datarate. For your case interpolation is 2x and clock rate is 1KHz so the data rate should be 500Hz.

    Secondly the there is a transformer at output of the DAC which has a lower output limit of 8 KHz. You are trying to output a very low frequency signal which is not passing through the transformer.

    To see the output from the DAC you will have to modify the DAC board as mentinon in userguide of the evm. here is the section of the user guide that show you how do the modifications.

    3.1.3.2 Unbuffered Differential Output
    To provide unbuffered differential outputs, the EVM must be configured as
    follows: remove R2, C20, C21, and T1; Install R3, R4, R7, R8, J1 and J6.

    Regards,
    Neeraj Gill