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DAC38RF87EVM: Working on Xilinx KCU105 but not on other evaluation modules.

Cody Emerson
Prodigy 40 points

Part Number: DAC38RF87EVM

My project works perfectly on the Xilinx KCU105 but not with boards made by other manufacturers. I have tried two separate boards and they both are losing CPLL lock in the GTH after I pulse SYSREF. Also after I pulse SYSREF, everything in my GTH zeroes out(reset_done,txdata,txcharisk) almost like the JESD core is put into reset.  It is not until I reset the JESD core that the CGS starts sending out the GTH and the CPLLs are in lock again. Lastly, I am never seeing in_sync go high.

Thank you

  • 0
    TI__Guru* 91947 points

    Cody,

    What are these other platforms? What LMF setting are you trying to operate with? Have you tried contacting the vendors of these other platforms for help?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 40 points

    Hey Jim

    HTG-K800 and S2C Quad KU. My LMF settings are 4,2,32. I am able to get sync on the HTG but when I do I get many Alarms(On all lanes): Error in CGS, running disparity, 8/10b lookup, and sometimes a bad RBD value. If I don't get sync, I just see FIFO read and write errors, and my GTH gets put into reset.

  • 0 in reply to Cody Emerson
    TI__Guru* 91947 points

    Cody,

    We have never used those other platforms. Have you tried using continuous SYSREF? Do any of the lanes have a polarity swap or  a different pin assignment on these other two boards?  If those boards are both Xilinx based, have you tried to contact Xilinx for support? They have a very helpful JESD section on their web site with many app notes and examples.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 40 points

    Hey Jim,

    I was able to get it to work but the FPGA has to be in reset before I press the reset JESD core and Start Sysref button in the GUI.  So my startup is:

    1. Hold FPGA in reset.

    2. Press Start sysref and reset DAC button in GUI

    3. Release reset after GUI button press

    I've been trolling the xilinx and JESD forums and haven't found a solution yet.

    Thanks