Hi,
I have been looking at the ADS8598H ADC with great interest.
According to the datasheet it has 8 simultaneously sampling 18bit ADCs at 500kSps. It has two serial data outputs (DOUTA and DOUTB) with a minimal sclk of 50ns.
When I calculate the time taken to read out all 8 channels I get: 8 channels x 18bit x 50ns clock / 2 data outputs = 3.6us = 278kSps! (not considering conversion time nor any other timings)
To me it looks like a typo in the datasheet, as the ADS8598S (with 200kSps) has exactly the same serial readout specifications (sclk = 50ns min.).
OR
The other explanation would be, that the maximal sampling rate of 500kSps can only be achieved by using the parallel read mode (in which case this should be mentioned in the datasheet).
Could someone from TI please clear this up for me.
Thanks,
Simon