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ADC124S101: Behavior at less than SCLK 16 pulses

Kenji Ninagawa
Expert 4190 points
Part Number: ADC124S101

Team,

 

Our customer is working on abnormal cases for ADC124S101.

 

Generally the device works in a spec that it completes 1 sequence (16 SCLK pulses) within XCS=Low.

Then, as one of abnormal cases, in case SCLK pulses are less than 16 at XCS=Low, which behavior in the attached file does the device take ?

 

/cfs-file/__key/communityserver-discussions-components-files/73/ADS124S101-behavior.xlsx

 

Thanks and Regards,

Metropolitan (Tokyo) Area FAE  Kenji Ninagawa


  • 0
    TI__Guru**** 168445 points
    Hi Kenji,

    The ADC124S101 uses the /CS as a means to start data acquisition, so case 2 would never be a valid condition. It is best practice to keep the SCLK consistent, so that a full cycle is completed. What conditions are present in this application that might cause varitions 1 and 2?
  • 0 in reply to Tom Hendrick
    TI__Expert 4190 points

    The customer is concerned about an abnormal condition, while of course they usually work to keep the SCLK consistent.

    Then, if SCLK pulses are less than 16 at XCS=Low, which behavior in the attached file does the device work at ?

     

    Ninagawa

  • 0 in reply to Kenji Ninagawa
    TI__Guru**** 168445 points

    Hi Kenji,

    As I mentioned, case 2 would not be a valid condition.  The conversion would re-sample after /CS goes high and the re-applied SCLK would always start at CLK 1.  Depending on how many clocks there are before /CS goes high, you may get a few valid bits out of the part.