TSW30SH84EVM: Working of LMK04800 control in tsw30SH84evm

You can check out the schematic in the design package on ti.com to trace out where all of the signals go.

CLK 4/5 supplies the DAC sample clock.
CLK 6/7 provides a clock to an SMA output
CLK 8/9 provides a clock to the FPGA fed through the TSW1400 connector

The internal VCO is programmed to something like 2457.6 MHz (likely a bit higher for the 'SH84) and the divider value divides that frequency to the required frequency for its function. The DAC clock, for example, is at a divide by 2 to get it in the 1.5 GSPS range.

--RJH