This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi.
I'm trying to program my ADS1298 and I got a problem with DRDY signal. He's pulsing after the RDATAC (4 ms as expected) and returning to low state. The triggering level is on 1.6V and my scope reads 4V on DRDY pin.
delay_ms(2000); // tpor
CS = 0;
SPIx_Write(0x06); // RESET
CS = 1;
delay_us(20); // 18 tclk
CS = 0;
SPIx_Write(0x11); // SDATAC
CS = 1;
delay_us(5);
CS = 0;
SPIx_Write(0x0A); //STOP
CS = 1;
delay_us(5);
SPIx_Write(0x41); //WREG
SPIx_Write(0x18); //24 values
SPIx_Write(0x86); //CONFIG1
SPIx_Write(0x10); //CONFIG2
SPIx_Write(0xC0); //CONFIG3
all other registers are 0x00, except GPIO (0xF0).
CS = 1;
delay_us(5);
CS = 0;
SPIx_Write(0x08); // START
CS = 1;
delay_us(5);
CS = 0;
SPIx_Write(0x10); // RDATAC
CS = 1;
delay_us(20);
tsclk = 500ns
DVDD=4V
AVDD=3.8V
What did I wrong? DRDY is telling me that new data is ready. But, after that, is DRDY must go to high state after CS = 0? Besides I double checked my INT pin, I predict that he still isn't working properly.
Thanks in advance,
Rhuan.
Hello Rhuan,
Thanks for your post.
DVDD = 4 V is beyond the allowed operational spec for this device. The maximum DVDD supply is 3.6 V with respect to DGND.
/DRDY will idle low when you are not reading the data. A few tCLK periods before the next sample is ready, /DRDY will return high so that the next falling edge occurs in line with the data rate period.
When you do read the data, /DRDY will be cleared and return high in sync with the first SCLK falling edge.
Best Regards,
Hi Ryan!
Thanks for your support. I checked my DVDD and I got 3,58V -- and i'm inside the absolut range of supply.
I tried all the resolutions and I saw the correct interval in ms between these pulses.
Once I read the ID, I believe that my CPOL and CPHA configurations are correct and the transmissions are occuring correctly.
What I'm still not understand is the behavior of DRDY. After the first CS = 0 before DRDY = 0, can DRDY behave like your explanation?
Thanks again!
Rhuan.