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ADS42JB69: Clarifications Needed

Part Number: ADS42JB69
Other Parts Discussed in Thread: LMK04828

Hi,

I plan on running 4 ADCs in a board. 

I am not too sure about the sync signals. Should they be ran from each ADC as in the diagram or should I send it to one ADC?

On page 34 of the datasheet it says: "L is the number of lanes per Lane". Should it say number of lanes per Converter?

I don't have much experience with JESD204b so any literature would come handy for me.

Thanks

  • Daniel,

    May I suggest you look into using the TI LMK04828 clock synthesizer that would be a perfect fit for your application. This device provides up to 7 pairs of device clock and SYSREF clock that you could connect to your 4 ADC's, the DAC and the FPGA. You need to route every SYNC signal from all ADC's to the FPGA if you plan on having all of these synchronized. You can go to the following link to download JESD material, including videos to help you understand this standard.

      

    Regards,

    Jim