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TLV2553: CLK falling edge to CS removal

Relay Man
Prodigy 70 points
Part Number: TLV2553

I am using the TLV2553 with a 400KHz data clock in a burst mode. I note the data sheet asks for a minimum hold of 0ns after the last falling edge of the clock. What would be the impact of a hold of -8.95 ns?

Thanks

  • 0
    TI__Mastermind 35550 points

    Hello,

    Thanks for your query on E2E.

    I think you are talking about th3 (Hold time CS low after last I/O CLOCK falling edge) as shown in section 6.8 and 6.9 (timing requirement) and Figure 33 as well, please correct me if I'm wrong. 0ns is a minimum timing requirement, which means /CS can be pulled back to high immediately at same moment as last available I/O Clock pulse and there is no any conflict in the reading and writing of data. There is no any impact to keep /CS low for longer time.

    Thanks.

    Best regards

    Dale

  • 0 in reply to Dale Li
    Prodigy 70 points

    Hi,

    I am using the device on a 3.3V supply, and I have a potential violation by 8.95 ns of the falling edge of the data clock to CS, is this an actual problem?

  • 0 in reply to Relay Man
    TI__Mastermind 35550 points
    No maximum timing limit for th3, there is no any issue to have longer /CS low signal after last falling edge of I/O CLOCK, I don't think this is a violation if you are talking about th3. Thanks.

    Best regards
    Dale
  • 0 in reply to Dale Li
    Prodigy 70 points
    The problem is that CS could be going high up to 8.95 ns before the last falling edge of the IO clock.
  • 0 in reply to Relay Man
    TI__Mastermind 35550 points
    I understand your issue now, I apologized for this misunderstanding. /CS can NOT go to high before the last edge of I/O CLOCK, otherwise, the ADC can't detect the last clock pulse, the last bit (LSB) on SDO will be missed if 8 or 12-Clock timing mode is used, also it will affect last bit data on SDI for 8-Clock transfer mode. For 16-Clock timing mode, the ADC will start the current conversion after the sixteenth falling edge of the current I/O CLOCK, so it will be affected as well if the last falling edge of the IO clock can't be detected. Thanks.
    Best regards
    Dale