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ADS42JB69: ADc and JESD issues

Part Number: ADS42JB69

Hi,

I am using ADC to provide adc samples to my FPGA zync processor(xc7z030sbg485 -1) at 250 msps sampling rate.

I have configured ti following way:

// set the ADC registers:
static const uint8_t spiAddress[] =
{
0x06,
0x07,
0x08,
0x0B,
0x0C,
0x0D,
0x0E,
0x0F,
0x10,
0x11,
0x12,
0x13,
0x1F,
0x26,
0x27,
0x2B,
0x2C,
0x2D,
0x30,
0x36,
0x37,
0x38

};

// set the ADC registers:
static const uint8_t spiData[] =
{
0x00,
0x00,
0x09,
0x04,
0x04,
0x00,//high freq selected if more then 250
0x00,//high freq
0xBB,//sine wave from adc
0x00,
0x00,
0x00,
0x00,
0x00,
0x06
0x03,
0x00,
0x00,//octets per frame F=1
0x13,//frames per multi frame K=8
0x00,
0xC0,
0x00,
0x00

};

am using jesd as subclass 0.

my queries are:

1. do i need to provide sysref to ADC input or not.

2.am not receiving any data output at receiver side.

How should i proceed .pl guide