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ADS42JB69: Unencrypted spice model for ADS42JB69

Prodigy 190 points

Replies: 5

Views: 541

Part Number: ADS42JB69

Hi,

Can you provide me the unencrypted spice model for the ADS42JB69?

Thanks,

Uttara

  • Hi Uttara

    No behavioral models (spice or other formats) are available for the ADS42JB69.

    We do have IBIS models available to verify signal quality of the digital I/O. Those are available here:

    http://www.ti.com/product/ADS42JB69/toolssoftware#simulationmodels

    We also have an Application Report which discusses how to correct the low-frequency response of the converter. That is available here:

    http://www.ti.com/product/ADS42JB69/technicaldocuments#doctype1

    I hope this is helpful.

    Best regards,

    Jim B

  • In reply to Jim Brinkhurst84999:

    Hi Jim,

    We do have the ibis model for this part but we wanted to verify something regarding the function of the SYSREF signals. Since ibis is not a through model we cannot verify this functionality so was wondering if we could get our hands on the spice model even if only for these pins.

    Thanks,
    Uttara
  • In reply to uttara sampath:

    Hi Uttara

    I'll see if there is anything else we can provide.

    Can you describe what you are trying to confirm regarding SYSREF?

    Is it related to the timing between SYSREF and CLKIN, or some other detail?

    Best regards,

    Jim B

  • In reply to Jim Brinkhurst84999:

    Hi Jim,

    We are looking to specifically simulate SYSREF and SYNC. We are driving SYNC using the DS90LV001. We had a conversation with an AE at TI (Mark Guastaferro) and initially he told us we can drive the SYNC pins with the DS90LV001 if they were a/c coupled because the common mode voltages do not align. A following email from Mark said that the ADC team pointed out a concern regarding a/c coupling of the SYNC signal. In typical applications the SYNC signal is only toggled a few times during the JESD204B initialization process. After synchronization it typically is turned off. Since it is not clocking for long periods of time the signals decay to common mode voltage on the ADC side of the decoupling caps. This can lead to an unstable condition with the receiver inputs. It is possible to place weak pull ups/downs on the ADC side of the decoupling caps to force a static condition. He also recommended active termination with DC coupling. We are trying to confirm the correct termination scheme for this scenario through simulation. So if you could provide the spice model atleast for SYNC we can simulate and verify the same while choosing the right termination.

    Thanks,
    Uttara
  • Guru 54260 points

    In reply to uttara sampath:

    Uttara,

    The signal Mark should have been describing above is SYSREF, not SYNC. Attached is the IBIS model for this device and another document showing an example of how to drive the SYNC and SYSREF signals.

    Regards,

    Jim

    ads42jb69.ibsADS42JB69_driving_sync_sysref.pptx

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