Other Parts Discussed in Thread: LMK04828
Hello,
I have a test setup using your ADC32J45EVM with your TSW14J50, using the ADC3000 SW to configure the ADC and LMK and using the high speed data converter pro software to analyse the ADC.
In some configurations I have Problems to establish the JESD-Link.
If I use an ADC input clock of 320 MHz I can use the clk divider inside the ADC to reduce the sample rate but when I reduce the ADC input CLK by increasing the clock divider of the LMK output it stops working.
I only have these Problems when I am using the ADC internal clock divider. It works just fine when I am not using the clock divider.
On my own hardware I have a 200 MHz clock and want to run the ADC with 100 Msps so I need the internal clock divider to work at that frequency.
I attached two configuration with the settings I used to run my 200 MHz /100 Msps setup. the first is without the ADC clock divider which works fine and the other one is wth the ADC clock divider set to 2 which I can't get to work.
Thank you for your help!
best regards
Torsten Bandel