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ADS127L01: Behaviour of sample conversion if START pin is tied to LOW

Part Number: ADS127L01

Hi Ryan,

ADC is configured to 32KSPS and DRDY interrupt duration is ~31 microseconds. I have a timing constrain to monitor the DRDY line and read the data sample within ~31microseconds with my microcontroller.

Without monitoring DRDY line, by pulling START pin to low and using RDATA (0x12) command I was able to read 24 bit data. Time delay between 8 bits to 8 bits is 37 microseconds as shown below.     

1. Is it possible to read samples using RDATA (0x12) command by pulling START pin to low. 

2. If yes, what would be the behaviour of output shift register on RDATA command. Does the 24 bits output register reloads for every ~31 microseconds or until the 24 bits are pushed out there wont be any reload. 

As we see 0x2A 0x38 0x46 is a valid data after decoding. But the I am curious to know  0x38 and 0x46 are not reloaded values. 

Thank you,

Best Regards,

Kiran

  • Hello Kiran,

    Thanks for your post and welcome to our forum!

    Let me first clarify how the START pin is used. START can be taken high by the MCU or pulled-up permanently with a resistor to DVDD to begin conversions. Alternatively, the START pin can be pulled / held low to stop conversions. When the START pin is held low, the MCU can also send the SPI op-code for START (08h) to start conversions and the op-code for STOP (0Ah) to stop conversions. Once conversions begin, you should leave the ADC running continuously as you collect data. Stopping the conversions resets the digital filter.

    The RDATA command (12h) only needs to be sent when you wish to read the same data again. Otherwise, you only need to send SCLKs in order to clock out the new data. In other words, writing 0x00 0x00 0x00 on DIN will clock out 24 bits of data on DOUT.

    kiran koneri said:

    As we see 0x2A 0x38 0x46 is a valid data after decoding. But the I am curious to know  0x38 and 0x46 are not reloaded values. 

    The data you've shown should be valid as long as a /DRDY falling edge does not occur during the data transfer.

    Best Regards,

  • Hi Ryan,

    Thanks for the quick and detailed response.

    We have a SW and HW constrain a) to monitor the DRDY line b) delay between the 8 SCLK pules is 37 microsecond as shown in the above screen shot.

    Ryan Andrews said:
    kiran koneri

    As we see 0x2A 0x38 0x46 is a valid data after decoding. But the I am curious to know  0x38 and 0x46 are not reloaded values. 

    The data you've shown should be valid as long as a /DRDY falling edge does not occur during the data transfer.

    Trying to read data samples using RDATA commands (Though previous samples data) by fixing START pin to GND (so no DRDY falling edges). With this setup there is continuous data sample responses. For example, if we send a sequence on DIN as 12h 00 00 00 12 00 00 00... we see the 24 bit + crc  for each 12h command as expected variable responses.

    The hardware OSR is configured to 32KSPS (~31microsec for 24 bits), and the delay between consecutive sclk 8 bits in our microcontroller is 37 microsecond (total time for 24 bits is 97 microseconds). In this case we would want to know the output shift register getting reloaded or not before pushing all the 24-bits on every 12h command.  

    Let me know if it is possible to read valid samples using op-code commands with the above constrains we have.

    Thank you,

    Best Regards,

    Kiran 

  • Hello Kiran,

    The RDATA command (12h) is decoded on the 8th SCLK falling edge. Meanwhile, the 8 bits that are read on DOUT while you send RDATA should be valid data from the previous output shift register contents. The 9th SCLK (first clock edge after RDATA) will clock out the MSB of the new data.

    Since you are holding the START pin low, are you sending the START command to collect data? Remember that you only need to send the START command one time for the ADC to convert continuously. While converting, you will see /DRDY toggle from high to low to indicate when new data is available. It will not stop until the STOP command is sent.

    Is there a reason that you cannot monitor /DRDY in your application? Have you considered the following alternatives?

    1. Reducing the data rate. This would allow your SPI transactions to complete between samples.
    2. Using a SAR ADC architecture to control precisely when conversions happen.

    Best Regards,

  • Hello Ryan,

    Thank you for the response. That solves our problem.

    I am sending the START command once in initialization process. Yes, but the throughput to monitor the drdy pin and respond with the sclk is in milliseconds. We are looking for an alternate micro in next version.

    Best Regards,
    Kiran