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ADC16DX370: JESD deterministic latency measurement

Part Number: ADC16DX370

Hi,

Tried verifying that JESD link latency is fixed between ADC16DX370 (on FMC142) and KC705 FPGA JESD Rx core. I am not bothered about exact latency value, I just want to confirm if the latency remains constant on reset or powercycle. Ideally JESD Subclass1 devices should have deterministic latency. Setup used to measure this latency is as follows:

1. Generated a square wave of frequency 1.4624999 MHz in FPGA. Its brought out onto a sma port and is given to oscilloscope(ch 2) and FMC142 A0 input through a splitter.

2. ADC output data is captured in FPGA and its MSB bit is brought out on to a sma port and given to oscilloscope(ch 3)

Timing between ch2 and ch3 signals in the oscilloscope give the latency. Latency measured is 1.249 us

As required, this latency remains constant on reset or power cycle.

But when I change the square wave frequency to 0.365624999MHz latency measured changes to 2.264 us.

Below are the snapshots of oscilloscope measurements for both the cases.

case 1 ( first image) case 2( second image) 

Blue waveform is the generated square wave from FPGA.

Pink waveform is the ADC MSB bit captured in FPGA.

Why is the latency changing with ADC input frequency? Shouldn't the latency be fixed for a given setup irrespective of ADC input signal.

Can you please let me know what could be the issue.

Thanks and Regards,

sumala

  • Hi Sumala,

    We are taking a closer look, and will be back with you soon.

    Best Regards,

    Dan
  • Hi Sumala

    From your oscilloscope photos it looks like you are starting the square wave after the ADC data link is already up and running.

    Is the generated square wave synchronized to the FPGA SYSREF input or LMFC signal? Could the phase offset between the LMFC and the generated square wave be different for the two different frequency square waves?

    If you have another SMA port available it would be useful to also capture the FPGA LMFC clock on the oscilloscope.

    Best regards,

    Jim B

  • Hi Jim,

    Yes, square wave starts only after ADC datalink is up and running. Starting of square wave is controlled by user using a dip switch. When the switch is made '1' only then square wave starts transmitting out of FPGA board. I make the switch only after the link is up.

    Generated square wave is actually MSB bit of output of a DDS(Direct Digital Synthesizer) block in FPGA. DDS generates a sine wave of required frequency. DDS block runs with a clock which is generated from the same source(LMK04828B) as device clk, sysref for ADC chip is generated. So Square wave is synchronous to device clock.  It does not use SYSREF input as such. In FPGA, LMFC clock is generated internally by the JESD IP core and not available to external as such. But there is a signal which indicates a first byte in every multiframe, so this signal is internally related to LMFC but not directly LMFC as per my understanding. I dont know if bringing out this signal on a sma would be of any use.

    I am unable to understand how the phase offset between LMFC and square wave can effect the delay, can you please elaborate..

    During the link establishment, sysref is used by ADC and FPGA to align their LMFC. Once their LMFCs are aligned and link is established, I am disabling sysref to ADC( SYS_EN='0').  FPGA JESD IP core uses sysref to align its LMFC counter on the first sysref event detected following reset and ignores subsequent events.So once the link is established, all my clocks are fixed, delays are fixed.

    Few observations made:

    freq=0.319999MHz delay=2.468us

    freq=0.36562499MHz delay=2.265us

    freq=0.3828306198MHz delay=2.201us

    freq=0.73124999MHz delay=1.581us

    freq=1.4624999MHz delay= 1.249us

    As frequency increases, delay is decreasing.

    Thanks and regards,

    sumala

  • Hi Jim,

    Just to understand if the staring phase of square wave will effect the latency measured:

    assume level '0' is indicated by 'a' level '1' is indicated by 'b'. so a square wave samples would be like "aaaabbbbaaaabbbb" or "aabbaabbaabb" depending on frequency.

    let the delay be 5 samples indicated by xxxxx

    Case 1: From the moment trigger is started let the square wave be
    aaabbbbaaaabbbb
    output waveform will be
    xxxxxaaabbbbaaaabbbb
    Delay from 1st b in square wave to 1st b in output waveform is 5 same as the delay of the link.

    Case2: assume the starting phase is different. Now let the square wave be
    aabbbbaaaabbbb
    o/p waveform would be: xxxxxaabbbbaaaa
    Even now delay from 1st b in square wave to 1st b in output waveform is 5.

    case 3: assume a different frequency
    aaaaaabbbbbbaaaaaabbbbbb
    o/p: xxxxxaaaaaabbbbbbaaaaaabbbbbb
    Even now delay from 1st b in square wave to 1st b in output waveform is 5

    plz correct me if my understanding is wrong. So if the delay of the link is fixed, ideally the starting phase should not cause the measurements to differ.

    Thanks and Regards,
    sumala
  • Hi sumala
    I agree with your reasoning. I don't see why there should be any difference in the delay between the waveforms even if their relationship to the LMFC timing is earlier or later. I'm still trying to understand what might be causing the difference.
    It is good that the delay is consistent from reset to reset or with power-cycles.
    I will discuss this with colleagues tomorrow to see if the can explain the delay variation seen.
    Best regards,
    Jim B
  • Hi Jim,

    The issue is resolved. 

    According to ADS16DX370 datasheet, For 2’s complement output, Vcm-Vref/2 will have 
    MSB ‘1’ and Vcm+Vref/2 will have MSB ‘0’. 

    Rising edge in ADC I/P waveform will correspond to a falling edge in ADC O/P MSB bit 
    and falling edge in ADC I/P waveform will correspond to a rising edge in ADC O/P MSB 
    bit. 

    So the Rising edge seen in O/P waveform corresponds to falling edge in I/P waveform. 

    Measured Δ=2.264 us. 
    Measured Δ is between the rising edges of I/P and MSB bit of O/P waveforms. 
    But rising edge in MSB bit of O/P corresponds to falling edge of I/P data. 
    So delay of the setup/link = Rising edge of O/P waveform - falling edge of I/P 
    waveform = Δ – T/2 =2.264 – 1.367 = 0.897us 

    Measured Δ=1.239 us. 
    Delay of the setup/link = Δ – T/2 =1.239 – 0.34176 = 0.897us 

    So latency/delay is constant. 

    Thanks and Regards,

    sumala