Hi,
Tried verifying that JESD link latency is fixed between ADC16DX370 (on FMC142) and KC705 FPGA JESD Rx core. I am not bothered about exact latency value, I just want to confirm if the latency remains constant on reset or powercycle. Ideally JESD Subclass1 devices should have deterministic latency. Setup used to measure this latency is as follows:
1. Generated a square wave of frequency 1.4624999 MHz in FPGA. Its brought out onto a sma port and is given to oscilloscope(ch 2) and FMC142 A0 input through a splitter.
2. ADC output data is captured in FPGA and its MSB bit is brought out on to a sma port and given to oscilloscope(ch 3)
Timing between ch2 and ch3 signals in the oscilloscope give the latency. Latency measured is 1.249 us
As required, this latency remains constant on reset or power cycle.
But when I change the square wave frequency to 0.365624999MHz latency measured changes to 2.264 us.
Below are the snapshots of oscilloscope measurements for both the cases.
case 1 ( first image) case 2( second image)
Blue waveform is the generated square wave from FPGA.
Pink waveform is the ADC MSB bit captured in FPGA.
Why is the latency changing with ADC input frequency? Shouldn't the latency be fixed for a given setup irrespective of ADC input signal.
Can you please let me know what could be the issue.
Thanks and Regards,
sumala