Hello,
Regarding to the Timing Requirement for SPI Interface on DAC104S085, The Timing for MIN is Greater than the Timing for the TYP which is not clear for me.
ex: for the SCLK Cycle Time Minimum Value should be 33 us and Typically it should be 25 us, Also it stated that T_actual Should be more than T_minimum and now T_typical is less than T_minimum.
also regarding given SPI Serial Timing Diagram
should we Enable the Sclk two Cycle Before de-asserting the ChipSelect(SYNC_n) or it is not required and the given waveform is OK.