Hi,
I want to ask about timing of LVDS DDR (Double Data Rate) outputs of the ADS4245 ADC.
In the datasheet tsu and th values are given for 160 MSPS.
The given tsu_min = 1.5 ns, th_min=0.3 ns values are very meaningful for the 160 MHz input clock. ( half of the clock period is 3.25 ns)
At this frequency it must be a bit complicated to capture ADC data correctly at the FPGA input.
As i know in order to correctly capture ADC data we must think about some design architectures like below:
**IBUFDS + IDELAY + IDDR primitevs on data paths.
**IBUFDS + IDELAY + (right combination of BUFIO/BUFR/BUFG and MMCM based clocking architecture)
**Choosing the right clock to feed the clock input of IDDR
**Changing the delay value of data IDELAY or clock IDELAY primitive (static or dynamic) to capture the data on the exact safe point on the data eye
**Constrainting the tsu and th values correctly in the constrains file of the HDL design
(set_input_delay constraints can be used for that purpose in Xilinx Vivado.
and set_input_delay values are dependent on the clock period and tsu/th values of the ADC)
**Maybe using a syncronization FIFO to feed the ADC data to the user logic part of the design
My main question is about the lower sampling frequencies.
We use the ADS4245 ADC in 10 MHz samling frequency. In the datasheet there are no exact values for that frequency.
In datasheet there is a lower frequency samling timing values section and in that section given values are like below:
65 MHz: tsu_min = 5.9 ns, th_min = 0.35 ns
80 MHz: tsu_min = 4.5 ns, th_min = 0.35 ns
125 MHz: tsu_min = 2.3 ns, th_min = 0.35 ns
Why are the th values are same while tsu values are becoming longer? Is this a datasheet errata or is th value all same for all frequencies?
How is the DDR data exactly comes relatively to the output clock in 10 MHz sampling frequency?
Must we still care about the shorter tsu and shorter th values?
At a first glance i decided not to use comlicated design and data is captured directly from IDDR primitive.
The clock input of IDDR is coming via BUFG which is at the center of FPGA. Input of BUFG is output clock of ADC.
IDDR is set to SAME EDGE PIPELINED mode in order to adjust the even/odd parts of the samples in the right place.
As i thought the half of the clock period is 50 ns. I set the input delay values around 15-20 ns.
At this configuration it seems to be working. Captured ADC data seems to be correct when i analyized it in ILA Debug Core in Vivado.
When i decided to make a review of the design i am thinking about to or not to change the design.
Do i need to make a complex design because of the shorter tsu and th values given even if i am working with 10 MSPS application?
Finally the exact tsu/th values for 10 MHz input clock will be fine for me and i can determine the design architecture.
If the tsu and th values are still shorter for 10 MHz input clock, what happens to data before and after the valid data positions.
(I was thinking that data must hold its last value until the change time will come.)
If the exact tsu/th values are not available for 10 MHz input clock can someone suggest about which design architecture to use for 10 MHz sampling frequency?
Any suggestions and comments will be fine for me.
Thanks.
Mustafa.
