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ADC12DJ3200: ADC12DJ3200 JESD RAMP TEST MODE SETTING

SANTANU KUMAR SINHA
Prodigy 175 points
Part Number: ADC12DJ3200
Other Parts Discussed in Thread: TSW14J57EVM

Dear Sir,

I'm using ADC12DJ3200 EVM with TSW14J57EVM.

  1. I need to know the parameters for setting the ADC into the JESD Test Mode ?  Preferably in Ramp Mode ?
  2. How the JESD ramp mode data is distributed across the lane during transmission ?
  3. What data is sent when "Enable Test Pattern Mode" is  enabled in Control Tab of ADC12DJxx00 GUI.
  4. Can we verify other JESD Test Mode in this setup ?  I tried. It was showing error.

I have attached the snapshot of setting done in ADC12DJxx00 GUI and the output observed in HSDC Pro software for your information. 

Thanks

With Regards,

Santanu Kumar Sinha

  • 0
    TI__Mastermind 44680 points
    Hi Santanu
    I am looking into your questions and will respond with more information shortly.
    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    TI__Mastermind 44680 points

    Hi Santanu

    Regarding your specific questions:

    1. I need to know the parameters for setting the ADC into the JESD Test Mode ?  Preferably in Ramp Mode ? All that is needed is to first disable the JESD204B block, select the desired test mode then re-enable the JESD204B block. Based on your screen shots it appears you have enabled it correctly.
    2. How the JESD ramp mode data is distributed across the lane during transmission ? As discussed below the pattern consists of a ramp in the 8-bit octets (see the Octet locations in Table 20 for JMODE0).
    3. What data is sent when "Enable Test Pattern Mode" is  enabled in Control Tab of ADC12DJxx00 GUI. Same answer as for 2. above.
    4. Can we verify other JESD Test Mode in this setup ?  I tried. It was showing error. Only some of the test modes can be used with the data capture firmware. Some test modes are only useful for direct hardware probing, etc. I would only recommend using the Short or Long Transport Test Patterns and the Ramp Test Pattern.

    The JESD204B RAMP test pattern consists of ramping of the octet values in each output data lane. This does not result in a very useful data pattern when translated into the 12-bit samples of JMODES 0, 1 2 or 3. 

    If you want to look at a test pattern in the 12-bit samples, it would be better to use the JESD204B Short Transport Test Pattern. That will give a repeating pattern of 12-bit data values as shown in Table 40 of the ADC12DJ3200 datasheet.

    Note that this table shows the values for all 16 lanes. If you are only using 8 lanes then ignore the information for lanes DA4-7 and DB4-7.

    Here is what JMODE0 data looks like for Short Transport Test pattern in HSDC Pro Time Domain View.

    I hope this is helpful.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 175 points

    Hi Jim,

    Thanks for the clarification.

    I was going through the options under JESD Test Mode in ADC12DJxx00 GUI. I got only Transport Layer Test Mode. When I enable that I am getting a waveform similar to waveform posted by you.

    1. How to enable Short or Long Transport Layer Pattern ? Is there any control for it ? How do I specify Short or Long Test Pattern ?
    2. Can u help me to understand the settings to enable the NCO's in this setup ?


    Thanks,

    WIth Regards,

    Santanu Kumar Sinha

  • 0 in reply to SANTANU KUMAR SINHA
    TI__Mastermind 44680 points

    Hi Santanu

    1. The type of Transport Layer Test Pattern is dependent on the data type in the particular JMODE. The JMODEs with 12 bit or 8 bit output will have Short Transport Test patterns. The JMODEs with 16 bit output will have Long Transport Test patterns. This is done in accordance with the JESD204B standard requirements.
    2. The NCOs are only utilized in specific JMODEs with dual inputs and decimation of 4, 8 or 16. The ADC sample rate should be selected so the desired input signal band is within one of the ADC Nyquist zones. The decimation factor should be selected so the DDC output bandwidth is wide enough to support the desired signal bandwidth. The MAX ALIAS PROTECTED SIGNAL BANDWIDTH information in Table 10 will be helpful to choose the decimation factor. Once the sample rate and decimation factor are decided you can set up the EVM using the following steps.
      1. Set the on-board clocking sample rate
      2. Set the desired JMODE for the decimation factor and output lane configuration. I recommend using JMODE 11, 14, or 16. These modes give the most flexibility and support the full clock frequency range of the device.
      3. Click Program Clocks and ADC button to configure the devices into the basic mode.
      4. On the NCO Configuration page, adjust the Preset 0 Frequency and/or Preset 0 Frequency values so that the NCO frequency is equal to the center frequency of the input signal band. This will shift the desired band of signals down to basedband for output by the decimation filters.

    I hope this is helpful.

    Best regards,

    Jim B