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ADS54J40EVM: Is the sampling rates available only a very select few options?

Part Number: ADS54J40EVM
Other Parts Discussed in Thread: LMK04828, ADS54J64, ADC32RF45EVM

I notice that when I select the config files for running the quick start procedure, I select the file with 983.04M sampling rate? I also note that other options are very specific - 122.88M,245.76M,307.2M,409.6M,450.56M,491.52M,614.4M,819.2M,983.04M and 1024M? Does this mean that I cannot select any other sampling rates that I might need, say a round 500M or 200M for that matter? 

  • Aravind,

    These default rates are based off of the 122.88MHz on-board VCXO. To get other frequencies like 500M, you will have to either provide an external clock source and operate the LMK04828 in clock distribution mode, or change out the VCXO to 100MHz part. The internal VCO of the LMK is locked to the 122.88MHz by default, so the values you are seeing are all factors of this frequency.

    Regards,

    Jim  

  • Thank you Jim!

    So if I do not want to alter the board and want to use the LMK04828 onboard and not an external clock, I will be limited by the available set of sampling frequencies. Am I correct in this understanding? I also have an adc32rf45evm and am looking towards an ADS54J64 quad channel EVM and I assume the same answer holds good for those as well? 

    Also, If I did use an external clock to get the 500MSPS rate, which config file would i choose in that case? I am not too sure on how to proceed in such cases where the sampling rate I need is different from the set of frequencies that you provide in the GUI

    When I save the raw data to the file, I see 9 nibble data in it. I cannot find the documentation on how I can parse these codes to the two channel raw data?

  • Aravind,

    The LMK is controlled by four tabs in all of the EVM GUI’s. These tabs, which are under the main LMK04828 tab, are shown in the attached presentation.

    The PLL1 Configuration tab sets the parameters to lock an external source or on-board 10MHz oscillator on most EVM’s, to the VCXO. In the example shown, there is a 10MHz oscillator coming in on CLKIN1 and a 122.88MHz VCXO connected to OSCIN. The PLL1 is locking these 2 sources together as follows:

    CLKIN1 / Clkin1 R divider = Oscin / N divider

    10MHz / 125 = 122.88MHz / 1536 = 0.08

    If you change either clock source, this equation must be made equal by changing the divider options.

    The PLL2 Configuration tab sets the parameters to lock one of the two LMK VCO’s with the VCXO. In the example shown, there is the VCXO coming in on the OSCin input and a feedback from one of the VCO's.  The PLL2 is locking these 2 sources together as follows:

    OSCin / (Doubler * R Divder) = VCO / (Prescalar * N divider)

    122.88MHz / 1 = VCO MHz / (2 * 12)

    VCO = 2949.12MHz.

    This VCO must be in the range specified by the data sheet. For the LMK04828, there is a VCO and a VCO1 option. The range for VCO is 2370MHz to 2630MHz. The range for VCO1 is 2920M to 3080MHz. You will notice in the tab that in the VCO Mux setting, VCO 1 is selected since the required frequency is 2949.12MHz.

    If an external clock is to be used, the VCO’s are bypassed and the clock present on CLKIN1 is routed to all of the outputs. In this case, the divider settings in both the Clock Outputs tab and SYSREF and SYNC tab usually need to be changed.

    The clock outputs tabs shows all of the divider settings for all DCLK outputs. CLKout2 is the device clock to the ADC. This has a divide of 3, which would send a 2949.12MHz/3 (983.04MHz) clock to the ADC.  Clkout 1 is used by the FPGA. In this example it is 245.76MHz.

    The last tab, SYSREF and SYNC, will set the frequency of all SYSREF outputs of the device.

    For information regarding downloading data, see section 3.1.1 of the High Speed Data Converter Pro GUI User's Guide which can be download from the web under the HSDC Pro product folder.

    Regards,

    Jim

    LMK_10MHz_122.88_PLL1_PLL2.pptx 

     

  • Thank you Jim for the detailed response. I will go through it in detail and get back to you in case I run in to any road blocks. Also the external clock signal to be supplied is a sine wave and not square wave at the required frequency, correct?
  • Aravind,

    Yes, we normally use a sine wave at about 10dBm from our signal generators.

    Regards,

    Jim

  • Jim

    I have looked through the section 3.1.1 of the HSDC Pro User's guide. It is mentioned in there that in case of multiple channel test cases for a bin file, the test file should be 16 bit interleaved data where channel-1 is the first sample, channel-2 the second sample etc. What I see inside the file is column of 9 nibble entries as follows.. I am not entirely sure how to interpret this data according to the section 3.1.1 of the HSDC Pro user guide.  Please clarify the same.

    537010175
    536748031
    536944642
    536879102
    536748033
    536748035
    536748030
    536616960
    536748030
    536944641
    536944640
    536748033
    537075711

  • Aravind,

    Are these hex values? Are you reading the bin file programmatically to get the values(537010175, 536748031,etc), if yes can we get the code they use to read the bin file?

    Regards,

    Jim

  • Jim

    I read the bin file created by HSDC Pro using MATLAB ( fopen and fread) and I get a column vector with these values. I believe these are hex values. Hence my question on how to make sense of these entries

  • Aravind,

    The Save option in HSDC Pro will save all channel data in Interleaved format as shown below. We use textpad (link below) software to view the bin file.

    Example of 2channel capture:

    [Ch1 Sample1 LSB byte][Ch1 Sample1 MSB byte] [Ch2 Sample1 LSB byte][Ch2 Sample1 MSB byte] [Ch1 Sample2 LSB byte][Ch1 Sample2 MSB byte] [Ch2 Sample2 LSB byte][Ch2 Sample2 MSB byte]..etc

    Regards,

    Jim

  • Jim

    This is the screenshot of the .bin file I am seeing when I open it with TextPad. According to your description, I should be reading this file as 216C, 1FFF, 2DE3, 1FFE, 27EC, 2000, 175E, 1FFF, 123C, 2000,1F5A, 2001 etc where 216C,2DE3, 27EC,175E,123C,1F5A... is channel 1 data and 1FFF,1FFE,2000,1FFF,2000... is channel-2 data? Am I right in this understanding?

  • Thanks Jim

    One more question. Since each channel data is 14 bits and here each channel data is 4 nibbles or 16 bits, which of the two bits are to be discarded to get the actual 14 bit data? Also if the ADC sample has hit the rails in either direction, what is the way to find it out? Is there an overflow bit available as part of the data stream? Where does one set this in the config file?
  • Jim

    Could you answer the above question/point me to the right document to find the answer to these questions?
  • Aravind,

    The upper 14 bits of the 16 bit data bus is used as the ADC output. The LSB of this bus can be programmed as an over range indicator. If the SDOUT or PDN pins are not used, these can be programmed to be over range indicators as well. This is all documented in the data sheet.

    Regards,

    Jim

  • Thanks Jim

    I assume programming these bits need to be done through the GUI. I am looking for documentation on how this is done with the GUI. Also in the default condition, are these two bits to be discarded then? ( as in they do not carry any meaningful information)?
  • Aravind,

    The GUI did not support this with buttons. You would have to go to the Low Level View tab and write to the registers manually.

    The 2 LSB's are discarded when in bypass mode but actually used in decimation mode.

    Regards,

    Jim