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Original question:

DAC37J82 register settings

DAC39J82: DAC38J82 register settings

Dmitri
Prodigy 235 points
Part Number: DAC39J82
Other Parts Discussed in Thread: LMK04828, DAC38J82,

Hello,

I am new to this DAC.

I have dac38j82 and lmk04828. I cannot figure out how to program these ICs even using the GUI provided by TI.

Could anyone provide the register settings relative to my case:

F = [1.5 ... 512]MHz

So Fdac = 1024MHz (minimum acording to Nyquist rule).

M=2

N=16

S=1 (is it Fdac = 1gsps ?,  as far as I understand I need 1.024gsps ?)

L = 4

F=1 (bytes per frame)

K=20(frames per multframe)

Lane rate = (M*N*1.25*S*F)/L = 2*16*1.25*1gsps*1/4=10gsps

Is it correct?

SYSREF = Fframe / K.

Is Fframe = Sample clock ?

SYSREF = 1024MHz/20 = 51.2MHz (max)

I would be gratefull if anyone provide register setting so that I could figure out what's going on in the DAC and understand the internal structure.

-Thanks in advance

  • 0
    TI__Guru* 91947 points

    Dmitri,

    I have attached two examples for you. One uses an external 1024MHz clock to the EVM and the other uses the on-board clock set to 1228.8MHz. I include register settings and GUI screen shots for both.

    Regards,

    Jim

    DAC38J82_Ext_Clk_LMFS_4211.cfgDAC38J82_Ext_Fs_1024_LMFS_4211.pptxDAC38J82_Fs_12288_LMFS_4211.pptxDAC38J82_LMFS_4211.cfg

  • 0 in reply to jim s
    Prodigy 235 points
    Hello Jim.

    Thanks a lot for the quick reply. That was very helpful.

    However we got some issues to clarify.

    In your first configuration with ext clock applied to DAC.

    Is it assumed that the input signal is complex meaning that the RF range is [-512..512]MHz?

    Is it possible in this configuration to feed DAC with 2 indepandant real signals?


    If not, would you be so kind to provide us the config for this case.


    I DACxxxx GUI in JESD Block pane the parameters are: L=4,M=2,F=1,K=20,S=1,N=16

    How did you calculate lane rate?

    Lane_rate = M*N*1.25*S*F/L = 2*16*1.25*1*1/4 = 10gsps

    but in your config it is 10.24gsps?

    What is S and F realy mean?

    F = bytes in frame?
    S = sample rate? Is it 1 or 1.024? according to datasheet this is the number of converter samples per frame.


    As far as I understood the internal PLLs are disabled. So DEVCLK is provided from LMK (this is an ext clock you mentioned in your reply)


    Thanks in advance.

    Best regards,
    Dmitri.
  • 0 in reply to Dmitri
    TI__Guru* 91947 points

    Dmitiri,

    Yes, you can send 2 independent real data streams to 2 DAC's.

    The lane rate calculation is as follows:

    Lane rate = (Fs * 10 * F) / S

    S = numbers of samples per frame

    F = Number of octets per frame.

    In external clock mode, the LMK is setup for clock distribution mode and is using the external clock as a direct input that then gets divided down by the clock output dividers.

    See attached document for help with JESD parameters such as S and F.

    Regards,

    Jim  

    JESD204B Overview July_2018.pptx

  • 0 in reply to jim s
    Prodigy 235 points

    Jim,

    Thanks a lot. JESD parameters are now understandable for me.

    last question, is there any document with clear explanation how to setup PLLs inside DAC for the desired Fdac (besides datasheet)?

    Regards,

    Dmitri.

  • 0 in reply to Dmitri
    TI__Guru* 91947 points

    Dmitri,

    We have a document we created for another part but most of it applies to the DAC39J82 as well.

    Regards,

    Jim

    PLL setup example.pdf

     

  • 0 in reply to jim s
    Prodigy 235 points

    Jim, many thanks. simple and clear. good.