This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC08D1020: Regarding accumulate noise

Part Number: ADC08D1020

I am using this device at 2 GSPS in Interleave mode.
When there is no analog input(only noise floor), and repeatedly accumulates at 100us cycle, 500MHz cyclic noise is generated with 100 times accumulate.

The amplitude of cyclic noise fluctuates slightly when calibration is executed.

Initially I thought that the 500 MHz operating clock on the digital circuit side was affected.
However, even if the analog / digital power supply of the ADC device is completely cut off and the analog power supply is supplied by another power supply device, it is generated.
Even if OV is changed and LVDS Vp-p is changed to 510mVp-p, the amplitude of this noise does not attenuate.
Therefore, now I think that it is not the influence of the digital circuit.

I have 2 questions:
- Is there a possibility of 500 MHz periodic noise due to the internal structure of the ADC08D1020?
In the case of Interleave mode, we thought that 1 GHz cyclic noise could be seen. I can not understand why it is 500 MHz cyclic noise.

- amplitude of 24 with accumulate of 100 times, amplitude of 49 with accumulate of 1000 times, is this reasonable for the performance of this device?

  • Hi user
    The ADC08D1020 has an interleaved architecture.
    The I and Q converters are each made up of 2 interleaved sub-converters. When operated in DES (dual edge sampling) or interleaved mode, there are a total of 4 interleaved sub-converters sampling the ADC input. Minor offset mismatch between these interleaved converters results in a spur at Fs/4. For 2 GSPS operation the Fs/4 spur is at 500 MHz. Proper device calibration will minimize the offset mismatch, but some amount will still remain. The spur level will also vary somewhat over time due to 1/f noise effects in the track and hold circuitry of the 4 interleaved converters.
    The ADC08D1020 datasheet doesn't describe the typical Fs/4 spur level. I can check on an evaluation board later today and let you know what is expected.
    Best regards,
    Jim B
  • Dear Jim B,

    Thank you for your information.
    I have been very happy because the cause of 500 MHz cycle noise has been clarified.