ADC08DJ3200: Possible to run the ADC08DJ3200 @ full rate (3.2 GSPS x 2 channels) with TSW14J56revD EVM board?

Steve Krupa

Part Number: ADC08DJ3200
Other Parts Discussed in Thread: ADC12DJ3200EVM, TSW14J57EVM, , , ADC12DJ3200, DAC38RF82

Hello TI High Speed ADC Application Support Engineers:

My team and I are currently evaluating the ADC12DJ3200EVM, paired with a TSW14J57 data capture card. We are running the ADC at full throttle (3.2 GSPS x 2 channels) in order to capture the I and Q components of our (~ 1.6 GHz BW) baseband signal. Our application requires periodic data capture of a pulsed signal, sent ~ every microsecond. Ideally, we would like to perform a (lengthy) series of triggered data captures which store the waveforms in memory until all available registers are full.... and then do a "bulk" data transfer to the host PC via USB3. Using the HSDCpro GUI interface, it is my understanding that the only way to re-arm the trigger for the next capture event is to save the contents of memory to the hard disk of the host PC (running HSDC pro). Is this correct/ still applicable? The latencies associated with these (mandatory?) file transfers will not support our desired (~1 microsecond) data capture frequency...

If we trigger the ADC on the first event and let it run continuously until the memory of the TSW14J57 is full (1x10^9 16-bit samples), we will max out the memory in ~ 313/2 ms. The divide-by-two arises from the need to run 2 channels simultaneously. We would like to extend the amount of time between file writes on the host PC as long as possible: is there any way we can intermittently accumulate waveform data in the memory of the TSW14J57 without accompanying data transfers to the host PC? In other words, we would like to perform the data capture in a pause/ resume fashion. Is there any way to do this using the TSW14J57 EVM board?

If the data capture pause/ resume feature cannot be realized using the TSW14J57EVM, is it possible to run the 8-bit version of the ADC at full rate (2 channels at 3.2 GSPS ) using the 14J56revD EVM? This data capture card has double the memory of the 14J57EVM. If so, would the pairing of an ADC08DJ3200EVM with the TSW14J56EVM give us 4GSamples worth of waveform storage before we max out the memory? This could be an interesting way to stretch out the time required between file transfers...

Thanks in advance for your help with these questions, the requirement of per-event data transfers/ file writes to the host PC under HSDCpro is a very critical issue for us at this time.

Sincerely,

Steve Krupa

over 5 years ago

0 Neeraj Gill over 5 years ago

TI__Mastermind 20541 points

Hi Steve,

I have sent your request to engineer responsible for this device and he will get back to you soon.

Regards,
Neeraj

0 Jim Brinkhurst1 over 5 years ago in reply to Neeraj Gill

TI__Mastermind 43930 points

Hi Steve
The TSW14J56EVM (Rev D or later) can support ADC08DJ3200 (or ADC12DJ3200EVM in 8-bit 8 lane modes) at 3200 MHz clock rate. You would select JMODE7 (8 bit, dual mode, 8 lanes). The ADC output sample rate setting in HSDC Pro will be 3.2 GSPS. The serial bit rate will be 3200 x 2.5 = 8 Mbps. This is within the capabilities of the TSW14J56EVM.
I did some testing in this configuration and have encountered some issue with the Ch2 data near the end of the data record. The maximum length I am successfully capturing in 2 ch mode (JMODE7) is 16,777,216 samples.
In single channel mode (JMODE5) I can capture up to 2,147,483,648 samples. The HSDC Pro firmware/.ini settings prevent entering larger data capture depths than this value.
Best regards,
jim B

0 Jim Brinkhurst1 over 5 years ago in reply to Jim Brinkhurst1

TI__Mastermind 43930 points

Hi Steve
To address your other question, there is currently no way to do multiple triggered captures gradually filling up the TSW14J57EVM memory, and then at the end of the sequence read out the data to the PC.
Best regards,
Jim B

0 Steve Krupa over 5 years ago in reply to Jim Brinkhurst1

Intellectual 300 points

Hi Jim,

Thanks so much for your quick and thorough answers to both of my questions.

I am very grateful for your testing of the TSW14J56 data capture card in both JMODE7 and JMODE5. Is the memory constraint in JMODE7 something that the TSW14J56 firmware team can fix in the near future? In a similar vein, is there any possibility of "forking" a variant of the JMODE5 firmware that would allow us to "max out" the available sample memory of the TSW14J56 for 8-bit samples? The sample limit you cited (2,147,483,648 ) reflects the usage case for 16-bit samples, correct? Shouldn't we be able to squeeze a lot more 8-bit sample data onto the TSW14J56 card, than this HSDC pro firmware/.ini encoded limit? This would be a great feature to demonstrate the utility of the ADC08DJ3200 chipset, for applications not requiring high precision in the waveform capture.

I will test out JMODE5 with our ADC12DJ3200 card, and see how much our waveforms change.

Thanks and Best Regards,

-steve

0 Jim Brinkhurst1 over 5 years ago in reply to Steve Krupa

TI__Mastermind 43930 points

Hi Steve

The firmware/software team is investigating the JMODE7 capture depth issue on Ch2. I see a similar behavior for JMODE2 (12 bits) which may help them locate the issue.

The capture firmware we use is generic in nature to allow support of many different JESD204B LMFS configurations. Unfortunately this also means that the memory storage mechanism used is not optimized well for samples less than 16 bits. I will ask if there is any easy way to improve the sample depth but I expect there isn't anything that can be done in the short term.

Another approach that might be worth considering is the reference firmware we have available for the ADC12DJ3200EVM with Altera Arria10 and Xilinx KCU105 development boards. That firmware is more optimized for 12 bit operation and you might be able to add processing, etc. to accomplish what is needed.

The firmware packages are available for download here in the Software section:

I hope this is helpful.

Best regards,

Jim B

0 Jim Brinkhurst1 over 5 years ago in reply to Jim Brinkhurst1

TI__Mastermind 43930 points

Hi Steve

The firmware team reports that the actual saved data in the .bin file is OK for Ch1 and Ch2 on TSW14J56. So you can get up to 1073741824 samples per channel in JMODE7 (8b dual channel).

Unfortunately there aren't any improved capture depth firmware builds available. The more real-world application firmware examples linked above are the best bet if you need something like this.

Let us know if there are any other questions we can help with.

Best regards,

Jim B

0 Steve Krupa over 5 years ago in reply to Jim Brinkhurst1

Intellectual 300 points

Hi Jim,

Thanks for checking out the capture-depth issue for different bit-length samples using the TSW14J56 EVM. Our long term goal is to develop a full custom FPGA solution for our application, but it's a huge help to work with the EVMs and GUIs supplied by TI to better understand the capabilities of the DAC and ADC devices currently available. We already have some important answers regarding the suitability of different operating modes for our Tx and Rx chains, which are advising future design decisions.

If you were to recommend a platform (KCU105 vs Arria10) for supporting the ADC12DJ3200 and DAC38RF82 EVMs, which of the two vendors (Xilinx or Altera) would you recommend? Let's assume the developer doesn't have any pre-existing "investment" with either of the vendors. I understand this is probably not a trivial decision, as you are effectively adopting a whole "ecosystem" of programming tools, IP solutions, and the like.

Your feedback and expert help have been really helpful with our design approach regarding data capture. I look forward to corresponding with you again on future issues which will undoubtedly arise... :)

Much Thanks,

-steve

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ADC08DJ3200: Possible to run the ADC08DJ3200 @ full rate (3.2 GSPS x 2 channels) with TSW14J56revD EVM board?