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TSW14J56EVM: Rev D

Part Number: TSW14J56EVM

Hi,
I am using a TSW40RF82EVM card with the configuration 2T2R_RevC_ConstInput_6xDec_12xInt_2949p12M_5898p2_4915p2Gb connected to a TSW14J56EVM card.
I generate on the DACs a succession of frequencies separated by zeros that I connect with the ADCs.
Can we synchronize the generation and the acquisition?
The noise between the generated frequencies is not constant

  • Hi Marcel,

    Would you like to trigger the ADC to start a capture in accordance with the DAC's non-zero output? The TSW14J56EVM has the ability to "self-trigger".

    Please see page 16 of this document which explains the triggering options.

    I would also suggest looking into our automation options since scripting may be helpful for your application. There is a MATLAB example using a very similar setup to yours at this link.

     

    More information in regard to the automation functions can be found in the HSDC Pro install folder.

    C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\HSDCPro Automation DLL\Manual and Examples

    Best Regards,

    Dan

  • Hello Dan,

    I have already tested according to page 16.
    I connected Trig out C to Trig in A
    Without trig enabled in HSDCPro, I read the data but the acquisition starts in the middle of the generated file and ends with the beginning.
    If I turn on "Trigger Mode Enable" then asks "Read DDR Memory" I have the indication Trigger absent

    Best regards,

    Marcel
  • Hi Marcel,

    I am working on a procedure for this, and will be back with you in a few days.

    Best Regards,

    Dan

  • Hi Marcel,

    Please follow the attached procedure for triggering the ADC with a pattern file.

    E2E Files.zip

    Best Regards,

    Dan

  • Hi Dan,


    Thank you for this information. I did different trials without success. I must make a mistake that I cannot locate.


    TSW40RF82EVM Config
    After loading the configuration file
    In the DAC38RF8x Quick Start tab
    • M = 4 to have a DAC Clock Frequency of 5896.24
    • 1 peer IQ
    • 4 Lanes
    • 12x to have an identical interpolation to the configuration file
    • PLL auto tune
    • Reset JESD Core DAC and SYSREF Trigger


    J3 and J9 connected
    INI files in place
    J 12 and J13 connected


    In HSDC Pro


    ADC tab
    • INI file selection ADC32RF80_8821T
    • Do you want to update: Yes
    • Frequency selection 2949.12M
    • ADC Input Frequency: 71.0475M
    • Decimation: 6
    • New lane rate .... To be set at 245.76M: Ok
    • Enable trigger: on


    DAC tab
    • Selection DAC38RF8x_841T
    • Loading Pattern File
    • Data Rate (SPS): 737.28M (I do not understand this value which does not seem compatible with the Tranceiver function)
    • Current Lane .... Set at 184.57M
    • Send: Ok
    • LED d2 flashes


    ADC tab
    • New lane rate is 9.8304G due to ADC changes. JESD reference clock from device EVM to TSW14J56revD needs to be set at 245.76M: Ok
    • TRGGER ARMED indication in Yellow
    • Read DDR Memory:
    • Connected in Green
    • No trigger occurred after 10 s
    I tried other configurations without success.

    Best regards

    Marcel

  • Hi Marcel,

    I am looking at this procedure again, and will be back with you soon.

    Best Regards,

    Dan
  • Hi Dan,

    Thank you.
    Do you know if a config file with 1 Transmit and 1 receive exist.

    Best Regards
    Marcel
  • Hi Dan

    I found an alternative for synchronization between generation and acquisition by using the second pair ADC / DAC but I am always interested in your solution.

    Best regards

    Marcel

  • Hi Marcel,

    Thank you for your patience. I am glad to hear that you have found an alternative solution. I am having issues with getting this to work myself, so I will post again when I have a verified solution.

    Best Regards,

    Dan