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Part Number: ADS4126
We used ads4126 to acquire signals， input clock is 125MHz ，and the DFS mode is complement/DDR LVDS LVDS. we used the test mode (register address 25h is configured to 04h value), the output signal i for d3p and d3n is as shown below, the rest of the LVDS data waveforms are similar. by the way, the cmos mode is no problem.
Please help confirm if this is a hardware issue or a software issue.
I do not see any issues with DP3 on our EVM. Are you also enabling the digital functions by writing a 0x08 to address 0x42? With address 0x25 set to 0x04 you should see a ramp. The ADC output pin for D3 is also used by D2 so you will see a couple of different levels (00, 01, 10, and 11) on this output.
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