Other Parts Discussed in Thread: LMK04828, LMX2592
Hi,
My question is regarding the programming sequence of ADC32RF45.
On page 112 of the data sheet in table 115 it says: first provide ADC with sysref and then hard reset pins 33 and 34. This confused me because pins 33 and 34 are sysrefp and sysrefn inputs and once I provide adc32rf45 with the sysref it automatically gets reset right? why do you explicitly say to hard reset the ADC? Or do you mean reseting pin 48 of the IC when you say hard reset? Also during programming the ADC should I keep sysref running? Because I am using continous sysref mode and I program LMK before programming ADC, thus sysref always runs while I am programming ADC32rf45 does this cause any problem? Should I turn sysref off right before programming the ADC?
I am asking these questions because I happen to have a problem with my setup from time to time. My setup has a carrier board with kintex ultrascale FPGA and a FMC board with LMK04828 LMX2592 and ADC32RF45 on it. Once power is on, FPGA is programmed with .mcs in the flash and first LMK is programmed through SPI. Then LMX is programmed and finally ADC32RF45 is programmed. I power off and on the system to see if ADC32RF45 establishes the link with the FPGA everytime I program the FPGA. 1 out of 6-7 tries FPGA can not synchronize with the ADC32RF45 (sync signal doesnt go high). And when sync is not established when I monitor the current drawn from 12V supply, I realize that it is about 200mA less than it was when sync between FPGA and the ADC32RF45 is established. Thus I am suspicious if ADC32RF45 is programmed correctly. I don't think I have any problem during the programming of LMK and LMX because I check the lock signals from LMK and LMX and they look just fine.
Any help is greatly appreciated.
Thank you.
