ADS54J60: sysref input signal with respect to DEVCLK

Hi, guys,

We are migrating from ADC12J2700 toADS54J60. When using ADC12J2700, we can use "RDEL" value to adjust the delay of the SYSREF input signal with respect to DEVCLK. Also, ADC12J2700 provide a "Dirty Capture" bit to indicate that a SYSREF rising edge occurred very close to the device clock edge. Using this feature, our team has been successfully and reliably find a ideal RDEL to sample the SYSREF using DEVCLK to reset the LMFC. However, I do not see this RDEL and Dirty capture detection feature using the new ADS54J60 which will pose us a big problem of finding a reliably "eye delay".

Is there a similar feature using ADS54J60?   

Thanks a lot for your help.