ADC34J45EVM: JESD parameters

Hi,

I tried to integrated ADC34J45EVM with FPGA kcu105. I did not received the "bcbcbcbc" data for Sync. I want to  know what the JESD interface parameters are after I loaded the  "ADC3xJxx_160MSPS_Operation_LMK_Setting.cfg", for I doubt that ADC and FPGA did not match well . For example:

1,  is subclass 0 or 1?

2,  numbers of frames per multiframe (K)

3,  Numbers of Octests per Frame (F)

4,  the number of lanes per link (L)

5, the max line rate

6, the frequency of the refclk

7,  the frequency of the jesd core clock

And inside the cfg file:

LMK04828
0x00 0x00
0x02 0x00
0x100 0x10

are the left column registers' address? and are the right column the configured registers's data?

Please tell me the above information or your opinion. Thanks a lot! 

Best,

Hong